On-chip semiconductor device having enhanced variability
A physical unclonable function (PUF) semiconductor device includes a semiconductor substrate extending along a first direction to define a length and a second direction opposite the first direction to define a thickness. At least one pair of semiconductor structures is formed on the semiconductor substrate. The semiconductor structures include a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first gate dielectric layer having a first shape that defines a first threshold voltage. The second semiconductor structure includes a second gate dielectric layer having a second dielectric shape that is reversely arranged with respect to the first shape and that defines a second threshold voltage different from the first threshold voltage.
1. A method of fabricating a physical unclonable function (PUF) semiconductor device, the method comprising:
forming a first gate dielectric layer having a first shape that defines a first dielectric area on a first active region of a semiconductor substrate, and forming a second gate dielectric layer having a second shape that defines a second dielectric area different from the first dielectric area on a second active region of the semiconductor substrate, the second shape reversely arranged with respect to the first shape;
forming a first semiconductor structure on the first gate dielectric layer to define a first threshold voltage of the first semiconductor structure, and forming a second semiconductor structure on the second gate dielectric layer to define a second threshold voltage of the second semiconductor structure that is different from the first threshold voltage.
2. The method of claim 1 , wherein forming each of the first gate dielectric layer and the second gate dielectric layer further comprises:
recessing a portion of the first gate dielectric layer to define a first dielectric layer portion of the first gate dielectric layer having a first thickness and a second dielectric layer portion of the first gate dielectric layer having a second thickness that is greater than the first dielectric layer portion of the first gate dielectric layer; and
recessing a portion of the second gate dielectric layer to define a first dielectric layer portion of the second gate dielectric layer having a first thickness and a second dielectric layer portion of the second gate dielectric layer having a second thickness that is greater than the first dielectric layer portion of the second gate dielectric layer.
3. The method of claim 2 , wherein forming each of the first gate dielectric layer and the second gate dielectric layer further comprises:
forming the first dielectric layer portion of the first gate dielectric layer to define a first length and the second dielectric layer portion of the first gate dielectric layer to define a second length that is different from the first length; and
forming the first dielectric layer portion of the second gate dielectric layer to define a first length and the second dielectric layer portion of the second gate dielectric layer to define a second length that is different from the first length.
4. The method of claim 3 , wherein forming each of the first gate dielectric layer and the second gate dielectric layer further comprises:
forming the first gate layer portion of the first semiconductor structure with a first thickness and the first dielectric layer portion of the second semiconductor structure with a second thickness that is different from the first thickness of the first semiconductor structure.
5. The method claim 4 , further comprising forming a plurality of pairs of semiconductor structures on the semiconductor substrate such that each pair of semiconductor structures has a threshold voltage differential that is different from one another.
6. A method of fabricating a physical unclonable function (PUF) semiconductor device, the method comprising:
forming a plurality of gate dielectric layers on a semiconductor substrate, each gate dielectric layer having a gate dielectric area that is reversely arranged with respect to one another; and
forming a semiconductor structure on each gate dielectric layer such that each semiconductor structure has a different threshold voltage defined by a respective gate dielectric area.
7. The method of claim 6 , further comprising randomly sizing each gate dielectric area to define random variations of the threshold voltages.
8. The method of claim 7 , wherein the forming a plurality of gate dielectric layers includes forming each gate dielectric layer with a first dielectric layer portion and a second dielectric layer portion different from the first dielectric gate portion.
9. The method of claim 8 , wherein the forming each gate dielectric layer further comprises forming the first dielectric layer portion having a first thickness and forming the second dielectric layer portion having a second thickness different from the first thickness.
10. The method of claim 9 , wherein the forming each gate dielectric layer further comprises forming the first dielectric layer portion having a first length and forming the second dielectric layer portion having a second length different from the first length.