Protective liner between a gate dielectric and a gate contact
A method of forming a protective liner between a gate dielectric and a gate contact. The method may include; forming a finFET having a replacement metal gate (RMG) on one or more fins, the RMG includes a gate dielectric wrapped around a metal gate, an outer liner is on the sidewalls of the gate dielectric and on the fins; forming a gate contact trench by recessing the gate dielectric and the outer liner below a top surface of the metal gate in a gate contact region; forming a protective trench by further recessing the gate dielectric below a top surface of the outer liner; filling the protective trench with a protective liner; and forming a gate contact in the gate contact trench, where the protective liner is between the gate dielectric and the gate contact.
1. A method comprising:
forming a finFET structure including a dummy gate on one or more fins, a gate spacer on sidewalls of the dummy gate, an outer liner on the gate spacer and on the fins, and a first inter-layer dielectric on the outer liner;
removing the gate spacer from at least a gate contact region;
replacing the dummy gate with a replacement metal gate, the replacement metal gate includes a metal gate and a gate dielectric, the gate dielectric is between the metal gate and the fins and between the metal gate and the outer liner;
forming a first fin contact through the first inter-layer dielectric and the outer liner, the first fin contact is in direct connection with the fins;
forming a gate contact trench by recessing the first inter-layer dielectric, the gate dielectric, and the outer liner in the gate contact region, the gate contact trench exposes the top surface of the metal gate;
forming a protective trench in the gate contact trench by recessing the gate dielectric exposing a portion of the metal gate sidewalls;
forming a protective liner in the protective trench; and
forming a gate contact in the gate contact trench, the gate contact is directly on the metal gate, and the protective liner is between the metal gate and the gate dielectric.
2. The method of claim 1 , wherein the protective liner is SiN.
3. The method of claim 2 , further comprising:
forming the protective liner on all surfaces in the gate contact trench; and
etching the protective liner from the top surface of the metal gate.
4. The method of claim 1 , further comprising:
forming a second inter-layer dielectric in at least a fin contact region and the gate contact region;
forming a fin contact trench in the second inter-layer dielectric exposing the top surface of the first fin contact; and
forming a second fin contact in the fin contact trench.
5. The method of claim 4 , wherein the second fin contact and the gate contact are formed during a single contact formation step.
6. The method of claim 1 , further comprising:
forming a gate contact liner between the gate contact and the metal gate.
7. The method of claim 6 , wherein the gate contact liner includes the protective liner.
8. The method of claim 7 , wherein the gate contact liner includes at least tantalum.
9. The method of claim 1 , wherein the gate contact is copper.
10. The method of claim 1 , wherein the gate spacer is a high-k material.
11. A method comprising:
forming a finFET structure including a dummy gate on one or more fins, a gate spacer on sidewalls of the dummy gate, an outer liner on the gate spacer and on the fins, and a first inter-layer dielectric on the outer liner;
forming a dummy gate trench by removing the dummy gate;
forming a replacement metal gate in the dummy gate trench, the replacement metal gate includes a metal gate and a gate dielectric, the gate dielectric is between the metal gate and the fins and between the metal gate and the outer liner;
forming a gate contact trench by recessing at least the first inter-layer dielectric, the gate dielectric, and the outer liner in a gate contact region, the gate contact trench exposes the top surface of the metal gate;
forming a protective trench in the gate contact trench by recessing at least the gate dielectric exposing a portion of the metal gate sidewalls;
forming a protective liner in the protective trench; and
forming a gate contact in the gate contact trench, the gate contact is directly on the metal gate, and the protective liner is between the gate contact and the gate dielectric.
12. The method of claim 11 , wherein forming the protective trench includes recessing the gate spacer in the gate contact region.
13. The method of claim 11 , further comprising:
forming the protective liner on all surfaces in the gate contact trench; and
etching the protective liner from the top surface of the metal gate.
14. The method of claim 11 , further comprising:
forming a gate contact liner between the gate contact and the metal gate.
15. The method of claim 14 , wherein the gate contact liner includes the protective liner.
16. The method of claim 15 , wherein the gate contact liner includes at least tantalum, the gate contact is copper, and the gate spacer is a high-k material.
17. The method of claim 11 , further comprising:
forming a first fin contact through the first inter-layer dielectric and the outer liner, the first fin contact is in direct connection with the fins, and the first fin contact is between two adjacent replacement metal gates.