Method of optimizing wire RC for device performance and reliability
A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.
1. A method comprising:
analyzing an integrated circuit design for an integrated circuit chip, said analyzing comprising determining Vmax for vias and metal lines in said integrated circuit design over a range of sizes for said vias and said metal lines, Vmax defining spacing between features on the integrated circuit chip due to time dependent dielectric breakdown based on device characteristics;
determining predicted use voltage for applications on said integrated circuit chip; and
tailoring one of the size and the location of at least one of said vias and said metal lines based on performance parameters of said integrated circuit chip.
2. The method according to claim 1 , further comprising:
comparing said predicted use voltage to said Vmax determined for said vias and said metal lines.
3. The method according to claim 1 , said tailoring comprising creating a modified circuit design based on performance parameters of said integrated circuit chip using selected sizes of said vias and said metal lines.
4. The method according to claim 3 , further comprising:
printing and etching said vias and said metal lines according to said modified circuit design.
5. The method according to claim 1 , said determining said predicted use voltage comprising using test and inline data to predict the use voltage that said integrated circuit chip will actually experience in applications.
6. The method according to claim 5 , said determining said predicted use voltage being done on lot, wafer, or chip basis.
7. A method, in a data processing system, of tailoring BEOL RC parametrics to improve chip performance, said method comprising:
analyzing, by said data processing system, a circuit design on a chip, said analyzing comprising determining Vmax for vias and metal lines in said circuit design over a range of sizes for said vias and said metal lines, Vmax defining spacing between features on the chip due to time dependent dielectric breakdown based on device characteristics;
determining, by said data processing system, predicted use voltage for applications on said chip;
comparing, by said data processing system, said predicted use voltage to Vmax determined for said vias and metal lines; and
creating a modified circuit design based on performance parameters of said chip, said modified circuit design using a lower voltage for Vmax.
8. The method according to claim 7 , further comprising:
tailoring, by said data processing system, one of the size and the location of at least one of said vias and said metal lines based on performance parameters of said chip.
9. The method according to claim 7 , further comprising:
printing and etching said vias and said metal lines according to said modified circuit design.
10. The method according to claim 7 , said determining said predicted use voltage comprising using test and inline data to predict the use voltage that said chip will actually experience in applications.
11. The method according to claim 10 , said determining said predicted use voltage being done on lot, wafer, or chip basis.
12. The method according to claim 7 , further comprising:
verifying said predicted use voltage being consistent with said lower voltage for Vmax.
13. The method according to claim 12 , said verifying further comprising:
determining frequency measurements of at least one performance sensitive ring oscillator (PSRO).
14. A method, comprising:
determining maximum voltages defining a range of sizes for spaces between vias and metal lines in an integrated circuit design due to time dependent dielectric breakdown based on device characteristics;
determining predicted use voltage for applications on an integrated circuit chip having said integrated circuit design; and
using said predicted use voltage to adjust one of the size and the location of at least one of said vias and said metal lines in said integrated circuit design according to said range of sizes for said spaces between said vias and said metal lines while keeping said predicted use voltage below the maximum voltage associated with a selected space.
15. The method according to claim 14 , further comprising:
creating a modified circuit design based on performance parameters of said chip, said modified circuit design using a predicted use voltage below the maximum voltage associated with said selected space.
16. The method according to claim 15 , said modified circuit design being based on performance parameters of said integrated circuit chip using selected sizes of said vias and said metal lines.
17. The method according to claim 15 , further comprising:
printing and etching said vias and said metal lines according to said modified circuit design.
18. The method according to claim 14 , said determining said predicted use voltage comprising using test and inline data to predict the use voltage that said integrated circuit chip will actually experience in applications.
19. The method according to claim 18 , said determining said predicted use voltage being done on lot, wafer, or chip basis.
20. The method according to claim 14 , further comprising:
verifying said predicted use voltage being consistent with a lower voltage for the maximum voltage associated with said selected space.