IP Library Granted Patent US 8,652,914
Granted Patent B2
US 8,652,914 · App. 13/039,678 · Granted Feb 18, 2014

Two-step silicide formation

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Quick Facts
Patent No.
US 8,652,914
App. No.
13/039,678
Granted
Feb 18, 2014
Kind
B2
Abstract

An aspect of the invention includes a method for forming a semiconductor device with a two-step silicide formation. First, a silicide intermix layer is formed over a source/drain region and a portion of an adjacent extension region. Any spacers removed to accomplish this may be replaced. Dielectric material covers the silicide intermix layer over the source/drain region. A contact opening for a via is etched into the dielectric material. A second silicide contact is formed on the silicide intermix layer, or may be formed within the source/drain region as long as the second silicide contact still contacts the silicide intermix layer.

Claims (25)

1. A method for forming a semiconductor device, the method comprising the steps of:

providing a transistor comprising a source/drain region, within a substrate, and having a portion of the source/drain region raised over the substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region;

forming a silicide intermix layer over the source/drain region, on a sidewall of the raised portion of the source/drain region, and over a portion of the extension region which is not covered by the dielectric spacer;

depositing dielectric material over the silicide intermix layer on top of the source/drain region;

creating a contact opening through the dielectric material, wherein the contact opening extends at least as far as the silicide intermix layer over the source/drain region; and

forming a silicide contact at the bottom of the contact opening.

2. The method of claim 1 , further comprising the step of removing an outer region of the dielectric spacer to expose part of the extension region.

3. The method of claim 2 , wherein the dielectric spacer comprises an inner spacer against the gate and outer spacer, and wherein the outer region removed is the outer spacer.

4. The method of claim 3 , further comprising the step of:

after forming the silicide intermix layer and before the step of depositing the dielectric material, replacing the outer spacer.

5. The method of claim 1 , wherein the step of forming the silicide contact at the bottom of the contact opening comprises the silicide contact consuming less than a length of the source/drain region.

6. The method of claim 1 , wherein the step of creating the contact opening comprises etching the contact opening past the silicide intermix layer into the source/drain region.

7. The method of claim 6 , wherein the silicide contact is a second silicide intermix layer.

8. The method of claim 1 , further comprising the step of:

after forming the silicide intermix layer, performing an annealing process to convert the silicide intermix layer to an epitaxial textured silicide.

9. A method for forming a semiconductor device, the method comprising the steps of:

providing a transistor comprising a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region;

forming a silicide intermix layer over both the source/drain region and a portion of the extension region which is not covered by the dielectric spacer;

depositing dielectric material over the silicide intermix layer on top of the source/drain region;

creating a contact opening through the dielectric material, wherein the contact opening extends past the silicide intermix layer into the source/drain region; and

forming a silicide contact at the bottom of the contact opening.

10. The method of claim 9 , wherein the silicide contact is a second silicide intermix layer.

11. The method of claim 9 , wherein the step of forming the silicide contact at the bottom of the contact opening comprises the silicide contact consuming less than a length of the source/drain region.

12. The method of claim 9 , further comprising the step of:

after forming the silicide intermix layer, performing an annealing process to convert the silicide intermix layer to an epitaxial textured silicide.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052561/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2011
From: ALPTEKIN, EMRE; JAIN, SAMEER HEMCHAND; VEGA, REINALDO ARIEL
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 025895/0127 →