Semiconductor devices with sidewall spacers of equal thickness
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
1. A method, comprising:
forming a first gate stack and a second gate stack over a fin structure;
forming a spacer material over the first gate stack and the second gate stack;
forming source and drain regions abutting the spacer material of the first gate stack;
forming a sidewall spacer for the first gate stack by depositing a liner material over the spacer material on sidewalls of the first gate stack, wherein the liner material of the first gate stack extends to an upper surface of the fin structure;
forming a sidewall spacer for the second gate stack by depositing the liner material over the spacer material on sidewalls of the second gate stack, wherein a portion of the spacer material formed over the second gate stack is not covered by the liner material, and wherein the liner material of the second gate stack is separated from the upper surface of the fin structure by the portion of the spacer material formed over the second gate stack which is not covered by the liner material; and
forming source and drain regions directly abutting sidewalls of the liner material of the second gate stack and the portion of the spacer material formed over the second gate stack which is not covered by the liner material.
2. The method of claim 1 , wherein the first gate stack is a PFET and the second gate stack is an NFET.
3. The method of claim 1 , further comprising forming of a space between the source and drain regions and the spacer material of the first gate stack by thinning the spacer material on sidewalls of the first gate stack and the second gate stack by an isotropic etching process.
4. The method of claim 3 , wherein the isotropic etching process comprises a chemistry of hydrofluoric ethylene glycol (HFEG) which is selective to SiN based spacer material.
5. The method of claim 3 , wherein the isotropic etching process comprises an HF-based wet chemistry for wet isotropic processes.
6. The method of claim 3 , wherein the isotropic etching process comprises an isotropic dry etch process used with NF 3 /NH 3 or NH 3 /HF based reactants.
7. The method of claim 3 , wherein the space has a width dependent on a thickness of the liner material.
8. The method of claim 1 , wherein the forming of the sidewall spacers comprises:
blanket depositing the spacer material over the first gate stack and the second gate stack;
forming the source and drain regions abutting the spacer material of the first gate stack; and
thinning of the spacer material over the first gate stack and the second gate stack to create a space between the source and drain regions and the spacer material of the first gate stack.
9. The method of claim 8 , wherein the forming of the sidewall spacers further comprises:
depositing the liner material over the spacer material of the first gate stack and the second gate stack, including within the space; and
removing the liner material and the spacer material formed on a substrate adjacent to the second gate stack.
10. The method of claim 1 , wherein the spacer material is provided in a blanket deposition process to a thickness of about 3 nm to 15 nm and the liner material is provided in a blanket deposition process to a thickness of about 1 nm to 5 nm.
11. The method of claim 1 , further comprising forming source and drain regions for the second gate stack, abutting the sidewall spacers of the second gate stack, wherein the source and drain regions of the first gate stack and the second gate stack are formed by an epitaxial growth process of semiconductor material, which is doped in-situ.
12. The method of claim 3 , wherein the liner material of the first gate stack extends into the space between the source and drain regions and the spacer material of the first gate stack to contact the upper surface of the fin structure.
13. The method of claim 12 , wherein the liner material of the first gate stack has a lower dielectric constant than a dielectric constant of the spacer material of the first gate stack.
14. The method of claim 13 , further comprising forming the space to have a width dependent on a thickness of the liner material, forming the spacer material to have a thickness of about 3 nm to 15 nm and forming the liner material to have a thickness of about 1 nm to 5 nm, wherein and the first gate stack and the second gate stack each include a dielectric layer formed in contact with an upper surface of the fin structure and in contact with inner walls of the spacer material, the dielectric layer being spaced apart from the liner material by the spacer material.
15. The method of claim 14 , wherein the first gate stack and the second gate stack each include a conductive material formed on the dielectric layer, the conductive material being in contact with inner walls of the spacer material, the conductive material being spaced apart from the liner material by the spacer material, and the liner material of the first gate stack extends into the space between the source and drain regions and the spacer material of the first gate stack to contact the upper surface of the fin structure.
16. The method of claim 15 , wherein the liner material is comprised of at least one of SiN, SiO 2 , SiOCN, SiCN and SiCOH.