FinFET with reduced parasitic capacitance
A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
1. A finFET semiconductor device comprising:
a plurality of fins etched from a semiconductor substrate;
a gate electrode above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gate electrode;
a self-aligned silicide contact positioned above and between active fin regions, wherein the self-aligned silicide contact has a stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being above the second upper surface; and
a metal contact above and in direct contact with the first upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the metal contact to the active fin regions.
2. The structure of claim 1 , wherein the active fin regions are completely covered by the self-aligned silicide contact such that the second upper surface of the self-aligned silicide contact is above the active fin regions.
3. The structure of claim 1 , wherein the first upper surface of the self-aligned silicide contact is substantially flush with an upper surface of a dielectric gate cap directly above the gate electrode.
4. The structure of claim 1 , wherein a contact area between the metal contact and the self-aligned silicide contact is equal to a surface area of the first upper surface of the self-aligned silicide contact.
5. The structure of claim 1 , wherein vertical sidewalls of the self-aligned silicide contact between the first upper surface and the second upper surface are substantially flush with vertical sidewalls of the metal contact.
6. The structure of claim 1 , further comprising:
an isolation region with an upper surface substantially flush with the first upper surface of the self-aligned silicide contact; and an interlevel dielectric layer covering the isolation region, the self-aligned silicide contact and the gate electrode, wherein a portion of the interlevel dielectric layer is below the upper surface of the isolation region and directly contacts a sidewall spacer separating the gate electrode from the self-aligned silicide contact.
7. A finFET semiconductor device comprising:
a plurality of fins etched from a semiconductor substrate;
a gate electrode above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gate electrode;
a self-aligned silicide contact positioned above and between active fin regions, wherein the self-aligned silicide contact has a stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being above the second upper surface; and
a metal contact above and in direct contact with the first upper surface of the self-aligned silicide contact.
8. The structure of claim 7 , wherein the active fin regions are completely covered by the self-aligned silicide contact such that the second upper surface of the self-aligned silicide contact is above the active fin regions.
9. The structure of claim 7 , wherein the first upper surface of the self-aligned silicide contact is substantially flush with an upper surface of a dielectric gate cap directly above the gate electrode.
10. The structure of claim 7 , wherein a contact area between the metal contact and the self-aligned silicide contact is equal to a surface area of the first upper surface of the self-aligned silicide contact.
11. The structure of claim 7 , wherein vertical sidewalls of the self-aligned silicide contact between the first upper surface and the second upper surface are substantially flush with vertical sidewalls of the metal contact.
12. The structure of claim 7 , further comprising:
an isolation region with an upper surface substantially flush with the first upper surface of the self-aligned silicide contact; and an interlevel dielectric layer covering the isolation region, the self-aligned silicide contact and the gate electrode, wherein a portion of the interlevel dielectric layer is below the upper surface of the isolation region and directly contacts a sidewall spacer separating the gate electrode from the self-aligned silicide contact.
13. A finFET semiconductor device comprising:
a plurality of fins etched from a semiconductor substrate;
a gate electrode above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gate electrode;
a self-aligned silicide contact positioned above and between active fin regions, wherein the self-aligned silicide contact has a stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being above the second upper surface; and
a metal contact on the first upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the metal contact to the active fin regions.
14. The structure of claim 13 , wherein the active fin regions are completely covered by the self-aligned silicide contact such that the second upper surface of the self-aligned silicide contact is above the active fin regions.
15. The structure of claim 13 , wherein the first upper surface of the self-aligned silicide contact is substantially flush with an upper surface of a dielectric gate cap directly above the gate electrode.
16. The structure of claim 13 , wherein a contact area between the metal contact and the self-aligned silicide contact is equal to a surface area of the first upper surface of the self-aligned silicide contact.
17. The structure of claim 13 , wherein vertical sidewalls of the self-aligned silicide contact between the first upper surface and the second upper surface are substantially flush with vertical sidewalls of the metal contact.
18. The structure of claim 13 , further comprising:
an isolation region with an upper surface substantially flush with the first upper surface of the self-aligned silicide contact; and an interlevel dielectric layer covering the isolation region, the self-aligned silicide contact and the gate electrode, wherein a portion of the interlevel dielectric layer is below the upper surface of the isolation region and directly contacts a sidewall spacer separating the gate electrode from the self-aligned silicide contact.