FinFET with reduced parasitic capacitance
A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
1. A method of fabricating a finFET semiconductor device, the method comprising:
forming a dummy gate above and perpendicular to semiconductor fins;
forming sidewall spacers on opposite sides of the dummy gate;
covering exposed portions of the semiconductor fins not covered by the dummy gate or the sidewall spacers with a dummy dielectric material;
forming an isolation region adjacent to and in direct contact with the dummy dielectric material, an upper surface of the isolation region is substantially flush with an upper surface of the dummy dielectric material;
replacing the dummy gate with a metal gate electrode covered by a dielectric gate cap;
replacing the dummy dielectric material with a self-aligned silicide contact, the self-aligned silicide contact being adjacent to and in direct contact with the sidewall spacers which separates it from the metal gate electrode, wherein the dummy dielectric material is removed selective to the isolation region, the sidewall spacers, and the dielectric gate cap;
forming a blanket metal layer on top of both the metal gate electrode and the self-aligned silicide contact, the blanket metal layer being in direct contact with the self-aligned silicide contact but physically isolated from the metal gate electrode by the dielectric gate cap;
patterning the blanket metal layer to form a source-drain contact;
removing excess material from the self-aligned silicide contact by recessing all of the self-aligned silicide contact except for a portion directly beneath the source-drain contact, wherein after recessing the self-aligned silicide contact has a stepped profile, the stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being in direct contact with the source-drain contact and above the second upper surface;
depositing an interlevel dielectric layer directly on top of the isolation region, the gate cap, and the second upper surface of the self-aligned silicide contact;
forming an opening in the interlevel dielectric and the gate cap to expose an upper surface of the metal gate electrode; and
forming a gate contact within the opening above and in direct contact with the metal gate electrode.