Semiconductor structures having low resistance paths throughout a wafer
A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
1. A structure, comprising:
at least one low resistance conduction path in a dielectric material, extending into an underlying substrate of a wafer, and within dicing channels of the wafer;
a barrier layer in direct contact with the low resistance conductive path; and
an electroplated seed layer in direct contact with the barrier layer;
wherein the at least one low resistance conduction path is a via lined with an oxide material layer, an adhesion layer and a copper layer.
2. The structure of claim 1 , wherein:
the via is filled with a metal material; and
the electroplated seed layer is provided in a patterned opening of the dielectric material.
3. The structure of claim 2 , wherein the low resistance conduction path is provided into an interlevel dielectric material and the underlying substrate.
4. The structure of claim 3 , wherein the at least one via is about 10 micron tall, with a resultant resistance of about 2 mΩ/□, and the seed layer is a copper seed layer with a thickness of about 10 nm with a resistance of about 18 Ω/□.
5. The structure of claim 1 , wherein the adhesion layer is one of Tantalum (Ta) or Titanium (Ti).