Local wiring in between stacked devices
Semiconductor devices and methods are provided to fabricate field effect transistor (FET) devices having local wiring between the stacked devices. For example, a semiconductor device includes a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer. The semiconductor device further includes a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration. The semiconductor device further includes one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.
1. A method for fabricating a semiconductor device, comprising:
forming a first field effect transistor (FET) device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer;
forming a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration, wherein forming the second FET device comprises:
forming a second drain region in contact with a first drain region;
forming an interconnect metal layer on a portion of a recessed first insulator layer and in contact with the first drain region and the second drain region;
forming the second gate structure over the second drain region; and
forming one or more conductive vias communicative with either the first gate structure of the first FET device or the second gate structure of the second FET device.
2. The method of claim 1 , wherein the first FET device is a PFET device and the second FET device is a NFET device.
3. The method of claim 1 , wherein forming the second drain region in contact with the first drain region comprises:
providing a plurality of nanowires extending from a surface of the semiconductor substrate, wherein a spacer is present on a top portion of sidewall surfaces of each nanowire and a hard mask is present on a top surface of each nanowire;
forming a second insulator layer over the recessed first insulator layer and the first drain region of the first FET device;
recessing the second insulator layer and exposing a portion of the sidewall of each nanowire and provide a recessed second insulator layer;
epitaxially growing the second drain region on at least a portion of the recessed second insulator layer and on the exposed sidewall portions of each nanowire; and
doping the second drain region with a dopant.
4. The method of claim 3 , wherein forming the second gate structure over the second drain region comprises:
depositing the interconnect metal layer on the recessed second insulator layer and to the top surface of the second drain region;
patterning the interconnect metal layer to provide for a device interconnect between each of the nanowires;
forming a first spacer layer on the recessed second insulator layer and over the top surface of the second drain region and patterned conductive metal layer;
forming the second gate structure over a top surface of the first spacer layer.
5. The method of claim 4 , wherein forming the second source region comprises:
forming a second spacer layer on a top surface of the second gate structure;
epitaxially growing the second source region on at least a portion of the second spacer layer and on the exposed sidewall portions of each nanowire; and
doping the second source region with a dopant.
6. The method of claim 5 , wherein forming the conductive via communicative with the first gate structure of the first FET device and the second gate structure of the second FET device comprises:
forming a third insulator layer on the second spacer layer and on a top surface of the second source region;
etching the third insulator layer, second spacer layer and the first and second metal gate structures to form a via in the third insulator layer, second spacer layer and the first and second metal gate structure, and
depositing a conductive material within the via.
7. The method of claim 5 , wherein the dopant for doping the second source region and second drain region is a P-type dopant material.
8. The method of claim 1 , wherein forming the conductive via communicative with the first gate structure of the first FET device and the second gate structure of the second FET device comprises:
etching the first and second metal gate structures to form a via in the first and second metal gate structure, and
depositing a conductive material within the via.
9. The method of claim 3 , wherein the hardmask is an oxidized hard mask.
10. The method of claim 1 , wherein the first FET device is a NFET device and the second FET device is a PFET device.
11. The method of claim 3 , wherein forming the first FET device comprises:
providing the plurality of nanowires extending from the surface of the semiconductor substrate, wherein the spacer is present on sidewall surfaces of each nanowire and a hard mask is present on a top surface of each nanowire; and a shallow trench isolation (STI) insulator deposited on the top surface of the semiconductor substrate;
forming a first source region on the semiconductor substrate;
removing the spacer from the sidewall surfaces of each nanowire;
forming the first gate structure over the first source region;
forming a first insulator layer over the first gate structure;
forming a second spacer on the sidewall surfaces of each nanowire;
recessing the first insulator layer and exposing a portion of the sidewall of each nanowire; and
forming a first drain region on the recessed first insulator layer and on the exposed sidewall portions of each nanowire.
12. The method of claim 11 , wherein forming the first source region comprises:
recessing the STI insulator and exposing a portion of the sidewall of each nanowire;
epitaxially growing the first source region on the recessed portion of the STI insulator and on the exposed sidewall portions of each nanowire; and
doping the first source region with a dopant.
13. The method of claim 12 , further comprising:
growing an oxide film on at least a portion of a surface of the doped first source region.
14. The method of claim 11 , wherein forming the first drain region on the recessed first insulator layer and on the exposed sidewall portions of each nanowire comprises:
epitaxially growing the first drain region on the recessed first insulator layer and on the exposed sidewall portions of each nanowire; and
doping the first drain region with a dopant.
15. The method of claim 1 , wherein the gate dielectric layer of the first gate structure comprises a high-k dielectric material.
16. The method of claim 1 , wherein the gate dielectric layer of the second gate structure comprises a high-k dielectric material.
17. The method of claim 1 , wherein the first drain region is an epitaxially grown.
18. The method of claim 1 , wherein the second drain region is an epitaxially grown.
19. The method of claim 1 , wherein the first insulator layer comprises a silicon based low-k dielectric material.
20. The method of claim 1 , wherein the interconnect metal layer comprises one of tungsten, nickel, cobalt, titanium or platinum.