Advanced chip to wafer stacking

1. A method of forming a 3D chip stack comprising:

forming a first bonding layer on a top surface of a first wafer, the first wafer comprising first chips having an upper surface coplanar with the top surface of the first wafer;

forming a second bonding layer on a top surface of a second wafer, the second wafer comprising second chips having an upper surface coplanar with the top surface of the second wafer;

separating the second chips from the second wafer;

placing the separated second chips in loading bays of a vacuum chuck, wherein a location of each of the loading bays is in a corresponding position to each of the first chips on the first wafer, the separated second chips are held in the loading bays using vacuum suction to a surface of the separated second chips opposite the second bonding layer, and each loading bay of the vacuum chuck comprises a plurality of moveable columns together providing a curved contact surface to hold the separated second chips;

bonding the second chips to the first chips by contacting the second bonding layer to the first bonding layer and using a bonding process creating a third bonding layer, wherein the third bonding layer includes the first bonding layer and the second bonding layer; and

depositing a dielectric over the bonded first chips and second chips.

2. The method of claim 1 , wherein a height difference between the center and the edges of the curved contact surface of each loading bay ranges from approximately 1 mm to approximately 5 mm.

3. The method of claim 1 , wherein the vacuum chuck includes a movable arm and the movable arm aligns each loading bay to the location of the first chips on the first wafer.

4. The method of claim 1 , further comprising:

cleaning the separated second chips in a cleaning chamber; and

activating the cleaned second chips before bonding the second bonding layer to the first bonding layer.

5. The method of claim 1 , further comprising:

forming a connecting line through the third bonding layer electrically connecting a first conductive connector of at least one of the first chips to a second conductive connector of at least one of the second chips.

6. The method of claim 1 , wherein the bonding process to create the third bonding layer is an oxide-to-oxide bonding process using a micro-scrubbing technique.

7. A method of forming a 3D chip stack comprising:

forming a first bonding layer on a top surface of a first wafer, the first wafer comprising first chips having an upper surface coplanar with the top surface of the first wafer;

forming a second bonding layer on a top surface of a second wafer, the second wafer comprising second chips having an upper surface coplanar with the top surface of the second wafer;

dicing the second wafer, including the second bonding layer, into individual second chips placing the individual second chips in loading bays of a vacuum chuck, each loading bay of the vacuum chuck comprises a plurality of moveable columns, the individual second chips are held by the moveable columns in each loading bay using a vacuum, and the position of each loading bay corresponds to a position of each of the first chips on the first wafer,

bonding the second chips to the first chips by contacting the second bonding layer to the first bonding layer and using a bonding process to create a third bonding layer, the third bonding layer includes the first bonding layer and the second bonding layer; and

depositing a dielectric over the bonded first chips and second chips.

8. The method of claim 7 , wherein the separated second chips are placed on a curved surface formed by the moveable columns within the loading bays.

9. The method of claim 7 , wherein the vacuum chuck includes a movable arm and the movable arm aligns each loading bay to the location of the first chips on the first wafer.

10. The method of claim 7 , further comprising:

cleaning the separated second chips in a cleaning chamber; and

activating the cleaned second chips before bonding the second bonding layer to the first bonding layer.

11. The method of claim 7 , further comprising:

forming a connecting line through the third bonding layer electrically connecting a first conductive connector of at least one of the first chips to a second conductive connector of at least one of the second chips.

12. The method of claim 7 , wherein the bonding process to create the third bonding layer is an oxide-to-oxide bonding process using a micro-scrubbing technique.

13. The method of claim 7 , wherein each loading bay is fitted with micro-motion controllers to adjust the position of each second chip within each loading bay.

14. A method of forming a 3D chip stack comprising:

forming a first bonding layer on a top surface of a first wafer, the first wafer comprising first chips having an upper surface coplanar with the top surface of the first wafer;

bonding a handler substrate to a top surface of a second wafer, the second wafer comprising second chips having an upper surface coplanar with the top surface of the second wafer;

thinning a bottom surface of the second wafer to expose the second chips;

forming a second bonding layer on the bottom surface of the second wafer;

dicing the second wafer separating second chips from one another;

debonding the individual second chips from the handler substrate;

placing the separated second chips in loading bays of a vacuum chuck, each loading bay of the vacuum chuck comprises a plurality of moveable columns, the individual second chips are held by the moveable columns in each loading bay using a vacuum, and the position of each loading bay corresponds to a position of each of the first chips on the first wafer;

bonding the second chips to the first chips by contacting the second bonding layer to the first bonding layer and using a bonding process to create a third bonding layer, the third bonding layer includes the first bonding layer and the second bonding layer; and

depositing a dielectric over the bonded first chips and second chips.

15. The method of claim 14 , wherein the separated second chips are placed on a curved surface formed by the moveable columns within the loading bays.

16. The method of claim 14 , wherein the vacuum chuck includes a movable arm and the movable arm aligns each loading bay to the location of the first chips on the first wafer.

17. The method of claim 14 , further comprising:

cleaning the separated second chips in a cleaning chamber; and

activating the cleaned second chips before bonding the second bonding layer to the first bonding layer.

18. The method of claim 14 , further comprising:

forming a connecting line through the third bonding layer electrically connecting a first conductive connector of at least one of the first chips to a second conductive connector of at least one of the second chips.

19. The method of claim 14 , wherein the bonding process to create the third bonding layer is an oxide-to-oxide bonding process using a micro-scrubbing technique.

20. The method of claim 14 , wherein each loading bay is fitted with micro-motion controllers to adjust the position of each second chip within each loading bay.