Advanced chip to wafer stacking
A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
1. A method of forming a 3D chip stack comprising:
providing a first wafer having first chips on a first substrate, the first chips include a first conductive connector, and the first chips have a coplanar top surface with a top surface of the first substrate;
providing a second wafer having second chips on a second substrate, the second chips include a second conductive connector, and the second chips have a coplanar top surface with a top surface of the second substrate;
forming a first bonding layer on the coplanar top surface of the first chips and the first substrate;
forming a second bonding layer on the coplanar top surface of the second chips and the second substrate;
separating the second chips from the second wafer;
placing the separated second chips in loading bays of a vacuum chuck, wherein a location of each of the loading bays is in a corresponding position to each of the first chips on the first wafer, the separated second chips are held in the loading bays using vacuum suction to a surface of the separated second chips opposite the second bonding layer;
bonding the second chips to the first chips by contacting the second bonding layer to the first bonding layer and using a bonding process creating a third bonding layer, wherein the third bonding layer includes the first bonding layer and the second bonding layer; and
depositing a dielectric over the bonded first chips and second chips.
2. The method of claim 1 , wherein the separated second chips are placed on a curved surface of the loading bay.
3. The method of claim 2 , wherein the first chips and the second chips each include defective dice and Known Good Dice (KGD).
4. The method of claim 3 , wherein KGD of the separated second chips are placed in the loading bays that correspond to KGD of the first chips.
5. The method of claim 1 , wherein the vacuum chuck includes a movable arm and the movable arm aligns each loading bay to the location of the first chips on the first wafer.
6. The method of claim 1 , further comprising:
cleaning the separated second chips in a cleaning chamber; and
activating the cleaned second chips before bonding to the second bonding layer to the first bonding layer.
7. The method of claim 1 , further comprising:
forming an connecting line electrically connecting the first conductive connector to the second conductive connector through the third bonding layer.
8. The method of claim 1 , wherein the bonding process to create the third bonding layer is an oxide-to-oxide bonding process.