Protective trench layer and gate spacer in finFET devices
Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer.
1. A method for forming a field effect transistor device, the method comprising:
forming a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin on a semiconductor substrate, the second semiconductor fin separated from the first semiconductor fin by a trench region having at least three sidewalls, wherein opposite facing sidewalls of the first semiconductor fin and the second semiconductor fin define first and second sidewalls of the trench region;
arranging a gate stack over the first semiconductor fin and over the second semiconductor fin, wherein a first sidewall of the gate stack adjacent to the trench region defines a third sidewall of the trench region;
depositing a protective layer on a top surface of the field effect transistor device, wherein the protective layer covers some or all of the top surface; and
removing a portion of the protective layer from the top surface of the field effect transistor device using an angled etching process, such that the protective layer remains only along at least the first sidewall of the gate stack and only on a bottom portion of the trench region in direct contact with the semiconductor substrate, wherein the protective layer along the first sidewall of the gate stack defines a gate spacer; wherein the removing the portion of the protective layer comprises:
directing a first ion beam generated by an ion beam source at the semiconductor substrate from a first direction at a first oblique angle, wherein the first oblique angle is measured clockwise from a vertical first axis extending perpendicular from a surface of the substrate to a second axis extending perpendicular from an emission point of the ion beam source, and wherein the first ion beam is perpendicular to a long axis of the first semiconductor fin and further comprising:
directing a second ion beam generated by the ion beam source at the semiconductor substrate from a second direction counterclockwise to the first direction at a second oblique angle, wherein the second oblique angle is measured from the vertical first axis extending perpendicular from the surface of the substrate to the second axis extending perpendicular from the emission point of the ion beam source, and wherein the second ion beam is perpendicular to the long axis of the first semiconductor fin.
2. The method of claim 1 , wherein the depositing further comprises conformally depositing the protective layer over the gate stack, the trench region, and over the first and second semiconductor fins, and
wherein the removing further comprises removing the protective layer from directly above the gate stack and directly above the first and second semiconductor fins and from the top portion of the trench region, wherein another portion of the protective layer remains along the first sidewall of the gate stack and on the bottom portion of the trench region along the first, second, and third sidewalls of the trench region.
3. The method of claim 1 , wherein the angled etching process comprises an ion milling process.
4. The method of claim 1 , wherein a material for forming the protective spacer comprises:
oxides, nitrides, oxynitrides, carbon-doped oxides, carbon-doped nitrides, or carbon-doped oxynitrides.
5. The method of claim 1 , wherein the protective layer is made from a silicon nitride material.
6. A method for forming a first and second field effect transistor (finFET) devices, wherein for each finFET device of the first and second finFET devices, the method comprises:
forming a first semiconductor fin and a second semiconductor fin on a semiconductor substrate, the second semiconductor fin being adjacent to the first semiconductor fin and separated from the first semiconductor fin by a trench region having at least three sidewalls, wherein opposite facing sidewalls of the first semiconductor fin and the second semiconductor fin define first and second sidewalls of the trench region;
arranging a gate stack over the first semiconductor fin and over the second semiconductor fin, wherein a first sidewall of the gate stack adjacent to the trench region defines a third sidewall of the trench region;
depositing a protective layer on a top surface of the finFET device, wherein the protective layer covers some or all of the top surface; and
removing a portion of the protective layer from the top surface of the finFET device using an angled etching process, such that the protective layer remains only along at least the first sidewall of the gate stack and only on a bottom portion of the trench region in direct contact with the semiconductor substrate, wherein the protective layer along the first sidewall of the gate stack defines a gate spacer,
wherein the first finFET device is n-doped (NFET device) and the second finFET is p-doped (PFET device), and wherein the angled etching process comprises a gas cluster ion beam (GCIB) process, and wherein the GCIB process comprises using a beam spot size defined by a Gaussian distribution of clusters with full width half maximum of approximately 1 cm in diameter, and a scanning step of 3 millimeters.
7. The method of claim 6 , wherein for each of the first and second finFET devices, the depositing further comprises conformally depositing the protective layer over the gate stack, the trench region, and over the first and second semiconductor fins, and
wherein the removing further comprises removing the protective layer from directly above the gate stack and directly above the first and second semiconductor fins and from the top portion of the trench region, wherein another portion of the protective layer remains along the first sidewall of the gate stack and on the bottom portion of the trench region along the first, second, and third sidewalls of the trench region.
8. The method of claim 7 , wherein the removing the portion of the protective layer further comprises:
isolating the NFET device using a first masking layer;
directing a first ion beam at the NFET device to remove the portion of the protective layer from the NFET device;
isolating the PFET device using a second masking layer; and
directing a second ion beam at the PFET device to remove the portion of the protective layer from the PFET device.
9. The method of claim 8 , wherein a composition of the first ion beam is different from a composition of the second ion beam.
10. The method of claim 9 , wherein a thickness of the protective layer of the NFET device is different from a thickness of the protective layer of the PFET device.