Channel silicon germanium formation method
A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second transistor area; growing an epitaxial layer on the second transistor area of the substrate; forming a trench in the substrate between the first transistor area and the second transistor area; performing a condensation technique to thermally mix materials of the epitaxial layer and the substrate; and filling the trench with a dielectric material to form a shallow trench isolation region between a first channel region of the first transistor and a second channel region of the second transistor; wherein performing the condensation technique is performed after forming the trench.
1. A semiconductor device, comprising:
a first transistor area arranged on a silicon support layer of a common substrate, the first transistor area comprising a buried oxide layer arranged on the silicon support layer, and a silicon layer arranged directly on the buried oxide layer;
a second transistor area arranged adjacent to the first transistor area on the silicon support layer of the common substrate, the second transistor area comprising a buried oxide layer arranged on the silicon support layer, and a silicon germanium layer arranged directly on the buried oxide layer; and
a trench arranged between the first transistor area and the second transistor area that extends to the silicon support layer of the common substrate;
wherein all of the buried oxide layer of the second transistor comprises an implant comprising silicon dioxide and a reaction product of an implanted ion of phosphorus or boron and silicon dioxide.
2. The semiconductor device of claim 1 , wherein the reaction product comprises silicon nitride, silicon oxynitride, or a combination thereof.
3. The semiconductor device of claim 1 , wherein the reaction product comprises borophosphosilicate glass.
4. The semiconductor device of claim 1 , wherein the first transistor area is a NMOS area, and the second transistor area is a PMOS area.