Microstructure modulation for metal wafer-wafer bonding

1. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:

providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and at least one first metallic bonding structure having a columnar grain microstructure and embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and at least one second metallic bonding structure having a columnar grain microstructure and embedded in the second bonding oxide layer; and

bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the at least one first and second metallic bonding structures, wherein during the bonding columnar grain growth is initiated and provides at least one columnar grain that extends across the another bonding interface that is present between the first and second metallic bonding structures.

2. The method of claim 1 , wherein the providing of the at least one first metallic bonding structure comprises:

providing a first opening in the first bonding oxide layer;

forming a first metallic bonding layer having a polycrystalline microstructure within the first opening and atop the first bonding oxide layer;

forming a first stress control layer on the first metallic bonding layer;

performing an anneal to convert the polycrystalline microstructure of the first metallic bonding layer into the columnar grain microstructure; and

performing a material removal process to remove the first stress control layer and the first metallic bonding layer located outside of the first opening.

3. The method of claim 2 , wherein the first stress control layer is composed of tantalum, tantalum nitride, titanium, titanium nitride, cobalt, cobalt nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, aluminum or aluminum nitride.

4. The method of claim 2 , wherein the annealing that converts said polycrystalline microstructure of the first metallic bonding layer to the columnar grain microstructure is performed at a temperature from 100° C. to 800° C.

5. The method of claim 4 , wherein the annealing is performed in nitrogen or a forming gas.

6. The method of claim 2 , wherein the material removal processes of the first metallic bonding layer located outside the first opening comprises chemical mechanical polishing.

7. The method of claim 2 , wherein the providing of the at least one second metallic bonding structure comprises:

providing a second opening in the second bonding oxide layer;

forming a second metallic bonding layer having a polycrystalline microstructure within the second opening and atop the second bonding oxide layer;

forming a second stress control layer on the second metallic bonding layer;

performing an anneal to convert the polycrystalline microstructure of the second metallic bonding layer into the columnar grain microstructure; and

performing a material removal process to removing the second stress control layer and the second metallic bonding layer outside of the second opening.

8. The method of claim 7 , wherein the second stress control layer is composed of tantalum, tantalum nitride, titanium, titanium nitride, cobalt, cobalt nitride, tungsten, tungsten nitride, ruthenium, ruthenium nitride, aluminum or aluminum nitride.

9. The method of claim 7 , wherein the annealing that converts said polycrystalline microstructure of the second metallic bonding layer to the columnar grain microstructure is performed at a temperature from 100° C. to 800° C.

10. The method of claim 9 , wherein the annealing is performed in nitrogen or a forming gas.

11. The method of claim 7 , wherein the material removal processes of the second metallic bonding layer located outside the second opening comprises chemical mechanical polishing.

12. The method of claim 1 , further comprising performing a pre-bake step prior to bonding, wherein the pre-back step is performed at a temperature from 100° C. to 700° C. in nitrogen or a mixture of nitrogen and hydrogen.

13. The method of claim 1 , wherein the bonding comprises:

performing wafer to wafer alignment;

bringing the first semiconductor structure into intimate contact with the second semiconductor structure; and

annealing at a temperature from 100° C. to 700° C. and in ambient including at least one of nitrogen, hydrogen, and helium.

14. The method of claim 1 , wherein each of the at least one first and second metallic bonding structures is composed of a metal or a metal alloy, wherein the metal or metal alloy is selected from copper, a copper-aluminum alloy, a copper manganese alloy, aluminum and an aluminum-copper alloy.

15. The method of claim 1 , wherein each of the first and second interconnect structures comprises at least one interconnect dielectric material and one or more interconnect metallic structures embedded therein.

16. The method of claim 15 , wherein the at least one or more interconnect metallic structures are composed of copper, a copper-aluminum alloy, a copper manganese alloy, aluminum or an aluminum-copper alloy.

17. The method of claim 15 , wherein the one or more interconnect metallic structures include a same metal or metal alloy as the at least one first and second metallic bonding structures.

18. The method of claim 1 , wherein each of the first and second bonding oxide layers is composed of silicon dioxide, tetraethylorthosilicate (TEOS), or fluorinated tetraethylorthosilicate (FTEOS).

19. The method of claim 1 , wherein the at least one first metallic bonding structure extends entirely through the first bonding oxide layer and contacts at least a portion of an interconnect metallic structure of the first interconnect structure, and the at least one second metallic bonding structure extends entirely through the second bonding oxide layer and contacts at least a portion of an interconnect metallic structure of the second interconnect structure.

20. The method of claim 1 , wherein each of the first and second semiconductor wafers comprises a semiconductor substrate containing one or more semiconductor devices thereon.