Laminate warpage control
A laminate includes a core, a buildup layer having a top and a bottom, the bottom contacting the core and a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask.
1. A method of forming a laminate, the method comprising:
providing a first laminate;
placing one or more electronic elements on a upper surface of the first laminate;
exposing the first laminate to heat;
determining locations of warpage on the upper surface;
receiving a second laminate; and
forming second laminate warpage control regions at locations on an upper surface of the second laminate that correspond to the location of warpage by removing portions of the upper surface.
2. The method of claim 1 , wherein the second laminate upper surface is a solder mask layer.
3. The method of claim 2 , wherein the second laminate warpage control regions are formed by removing portions of the solder mask layer.
4. The method of claim 2 , wherein the second laminate warpage control regions are formed by adding dielectric material to the solder mask layer.
5. The method of claim 2 , wherein the second laminate warpage control regions is a 5 μm×5 μm square.
6. The method of claim 2 , wherein the second laminate warpage control regions includes an outer boundary and are formed by removing portions of the solder mask layer within the outer boundary and adding dielectric material to the solder mask layer within the outer boundary.
7. The method of claim 1 , further comprising;
adding one or more electronic elements to the second laminate upper surface.
8. The method of claim 7 , further comprising:
exposing the second laminate to heat.
9. The method of claim 8 , wherein exposing the second laminate to heat includes a reflow process.
10. A laminate comprising:
a core;
a buildup layer having a top and a bottom, the bottom contacting the core; and
a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask, wherein the at least one warpage control region is a depression formed in the solder mask.
11. The laminate of claim 10 , wherein at least one of the at least one warpage control regions is a 5 μm×5 μm square.
12. The laminate of claim 10 , wherein at least one of the at least one warpage control region includes an outer boundary and is formed by removing portions of the solder mask layer within the outer boundary and adding dielectric material to the solder mask layer within the outer boundary.
13. The laminate of claim 10 , further comprising;
one or more electronic elements disposed on the top surface.
14. The laminate of claim 13 , wherein the electronics elements include a die and a capacitor.