Confined eptaxial growth for continued pitch scaling
A technique relates to manufacturing a finFET device. A plurality of first and second semiconductor fins are formed on a substrate. Gate stacks are formed on the substrate, each including a gate, a hard mask and an oxide layer. A dielectric spacer layer is deposited. A sacrificial fill material is deposited on the finFET device and planarized. A second hard mask is deposited, a trench area is patterned in the hard mask parallel to the first and second semiconductor fins, and the sacrificial fill material is anisotropically etched to create a trench. A dielectric wall is formed in the trench and the second hard mask and sacrificial fill material are removed.
1. A CMOS transistor comprising:
a first transistor comprising a plurality of first semiconductor fins patterned on a substrate, and a first transistor active area,
a first epitaxial layer on the first transistor,
a second transistor comprising a plurality of second semiconductor fins patterned on a substrate and a second transistor active area,
a second epitaxial layer on the second transistor,
at least two gate stacks arranged over channel regions of the first and second semiconductor fins, and
a dielectric wall having four vertical surfaces forming a rectangular profile formed of a first surface, a second surface, a third surface, and a fourth surface, wherein the dielectric wall is positioned in between the first transistor active area and the second transistor active area and extending between two of the at least two gate stacks, wherein the dielectric wall contacts one of the at least two gate stacks with the first surface and the other of the at least two gate stacks with the second surface and wherein the third surface faces the first transistor active area and the fourth surface faces the second transistor active area,
wherein the first epitaxial layer is confined to the first transistor by the dielectric wall.
2. The CMOS transistor according to claim 1 , wherein the dielectric wall is substantially perpendicular to the gate.
3. The CMOS transistor according to claim 1 , wherein the first transistor is an nFET transistor and the second transistor is a pFET transistor.
4. The CMOS transistor according to claim 1 , wherein the first epitaxial layer is adjacent to the dielectric wall of the first transistor.
5. The CMOS transistor according to claim 4 , wherein the first epitaxial layer does not physically contact the second transistor.
6. The CMOS transistor according to claim 1 , wherein the dielectric wall has a height that is greater than a height of the first transistor fins and a height of the second transistor fins.
7. The CMOS transistor according to claim 1 , wherein the second epitaxial layer is confined to the second transistor.