Enhancement of iso-via reliability
A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line.
1. A process of making a semiconductor structure comprising:
forming a wiring line;
forming a recess in the wiring line;
filling the recess with a reliability enhancement material;
forming a cap layer over the wiring line and the recess;
forming an interlayer dielectric (ILD) layer on the cap layer;
forming a via opening through the ILD layer, cap layer and reliability enhancement material to expose a surface of the wiring line; and
filling the via opening with a metal to form a metal-filled via in contact with the wiring line;
wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line.
2. The process of claim 1 wherein the reliability enhancement material is deposited so as to be compressive.
3. The process of claim 1 further comprising after forming a reliability enhancement material, treating the reliability enhancement material so as to be compressive.
4. A process of making a semiconductor structure comprising:
forming a wiring line;
forming a recess in the wiring line;
forming a reliability enhancement material on the wiring line, wherein forming the reliability enhancement material includes forming the reliability enhancement material in the recess;
forming an interlayer dielectric (ILD) layer on the wiring line;
forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and
filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via;
wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line and wherein the reliability enhancement material surrounds the metal-filled via only where the metal-filled via contacts the wiring line.
5. The process of claim 4 wherein prior to filling the via opening further comprising forming a barrier layer on a via wall between the via wall and the metal filling the via such that the barrier layer becomes a part of the metal-filled via.
6. The process of claim 4 wherein the reliability enhancement material is selected from the group of materials consisting of silicon nitride, silicon carbide and silicon carbide nitride.
7. The process of claim 4 further comprising forming a cap layer on the wiring line and wherein the step of forming the via opening includes forming the via opening through the cap layer.
8. A process of making a semiconductor structure comprising:
forming a wiring line;
forming a recess in the wiring line;
forming a reliability enhancement material on the wiring line, wherein forming the reliability enhancement material includes forming the reliability enhancement material in the recess;
forming an interlayer dielectric (ILD) layer on the wiring line;
forming only a single via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and
filling the via opening with a metal to form only a single metal-filled via in contact with the wiring line wherein the metal-filled via is an iso-via such that there is only one metal-filled via per the wiring line;
wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line and wherein the reliability enhancement material surrounds the metal-filled via only where the metal-filled via contacts the wiring line.