IP Library Granted Patent US 9,673,064
Granted Patent B2
US 9,673,064 · App. 14/874,393 · Granted Jun 6, 2017

Interposer with lattice construction and embedded conductive metal structures

Inventors: Jean Audet (Granby, CA); Benjamin V. Fasano (New Windsor, NY); Shidong Li (Poughkeepsie, NY)
Assignee: International Business Machines Corporation
H01L21/486H01L21/0274H01L23/15H01L23/49816H01L23/49827H01L23/49838H01L23/49894H01L25/0655H01L2924/0002
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,673,064
App. No.
14/874,393
Granted
Jun 6, 2017
Kind
B2
Abstract

A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

Claims (18)

1. An interposer comprising:

a lattice structure comprising a non-silicon interposer material and having a plurality of unit cells, wherein each unit cell of said plurality of unit cells extends below a topmost surface of said non-silicon interposer material and includes a plurality of conductive structures embedded in, and laterally surrounded by, a dielectric material, wherein a topmost surface of said lattice structure is coplanar with a topmost surface of said dielectric material.

2. The interposer of claim 1 , wherein said non-silicon interposer material has a thermal coefficient of expansion from 0 ppm/° C. to 15 ppm/° C.

3. The interposer of claim 2 , wherein said non-silicon interposer material is glass.

4. The interposer of claim 1 , wherein each unit cell of said plurality of unit cells is a square, a rectangle, or a triangle.

5. The interposer of claim 1 , wherein said conductive structure comprises a first conductive structure in direct contact with sidewall surfaces of said dielectric material and within each hole, another dielectric material in direct contact with sidewall surfaces of said first conductive structure, and a second conductive structure in direct contact with sidewall surfaces of said another dielectric material.

6. The interposer of claim 5 , further comprising a further dielectric material in direct contact with sidewall surfaces of said second conductive structure, and a further conductive structure in direct contact with sidewall surfaces of said further dielectric material.

7. A semiconductor structure comprising:

a non-silicon interposer disposed between a first substrate and a second substrate, wherein said non-silicon interposer comprises a lattice structure comprising a non-silicon interposer material and having a plurality of unit cells, wherein each unit cell of said plurality of unit cells extends below a topmost surface of said non-silicon interposer material and includes a plurality of conductive structures embedded in, and laterally surrounded by, a dielectric material, wherein a topmost surface of said lattice structure is coplanar with a topmost surface of said dielectric material.

8. The semiconductor structure of claim 7 , wherein said non-silicon interposer material has a thermal coefficient of expansion of from 0 ppm/° C. to 15 ppm/° C.

9. The semiconductor structure of claim 8 , wherein said non-silicon interposer material is glass.

10. The semiconductor structure of claim 7 , wherein each unit cell of said plurality of unit cells is a square, a rectangle, or a triangle.

11. The semiconductor structure of claim 7 , wherein said conductive structure comprises a first conductive structure in direct contact with sidewall surfaces of said dielectric material and within each hole, another dielectric material in direct contact with sidewall surfaces of said first conductive structure, and a second conductive structure in direct contact with sidewall surfaces of said another dielectric material.

12. The semiconductor structure of claim 7 , further comprising a further dielectric material in direct contact with sidewall surfaces of said second conductive structure, and a further conductive structure in direct contact with sidewall surfaces of said further dielectric material.

13. The interposer of claim 1 , wherein each unit cell extends entirely through said non-silicon interposer material.

14. The interposer of claim 1 , wherein each unit cell has a bottommost surface that exposes a sub-surface of said non-silicon interposer material.

15. The interposer of claim 1 , wherein a first set of said unit cells extends entirely through said non-silicon interposer material, while a second set of said units cells extends partially through said non-silicon interposer material.

16. The interposer of claim 1 , wherein each unit cell is a hole located in said non-silicon interposer material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052561/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2015
From: AUDET, JEAN; FASANO, BENJAMIN V.; LI, SHIDONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036721/0562 →
Continuity (2)
Division 14571352 · Dec 16, 2014
Related Publication 20160172290A1 · Jun 16, 2016