Transistor with robust air spacer
Fabricating a transistor includes receiving a semiconductor structure including a source/drain, a gate, and a spacer disposed between the source/drain and the gate, a trench contact disposed on the source/drain, a self-aligned cap disposed on the gate, and an interlevel dielectric layer disposed on the spacer, self-aligned cap, and trench contact. A source/drain contact is formed within the interlevel dielectric layer in contact with the trench contact and forming a gate contact in contact with the gate. The interlevel dielectric layer is removed from the spacer, self-aligned cap, and source/drain contact. The self-aligned cap and the spacer is selectively etched. A dielectric liner of a first dielectric material is deposited upon a top of the gate, the trench contact and the S/D contact. The first dielectric material of the dielectric liner pinches off a gap between the gate and the trench contact to form an air spacer therebetween.
1. A method of fabricating a transistor comprising:
receiving a semiconductor structure, the semiconductor structure including a source/drain, a gate, and a spacer disposed between the source/drain and the gate, the semiconductor structure further including a trench contact disposed on the source/drain and a self-aligned cap disposed on the gate, the semiconductor structure further including an interlevel dielectric layer disposed on the spacer, self-aligned cap, and trench contact;
forming a source/drain contact within the interlevel dielectric layer in contact with the trench contact;
forming a gate contact within the interlevel dielectric layer in contact with the gate;
removing the interlevel dielectric layer from the spacer, self-aligned cap, and source/drain contact;
selectively etching the self-aligned cap and the spacer; and
depositing a dielectric liner of a first dielectric material upon a top of the gate, the trench contact and the S/D contact, the first dielectric material of the dielectric liner pinching off a gap between the gate and the trench contact to form an air spacer therebetween.
2. The method of claim 1 , further comprising:
depositing a second dielectric material upon the dielectric liner.
3. The method of claim 2 , wherein the second dielectric material includes an oxide.
4. The method of claim 2 , wherein the second dielectric material includes a low dielectric constant (low-K) material.
5. The method of claim 1 , wherein the selective etching of the self-aligned cap includes substantially removing the self-aligned cap.
6. The method of claim 1 , wherein the selective etching of the spacer includes removing a portion of the spacer.
7. The method of claim 1 , wherein the first dielectric material includes a non-conformal dielectric material.
8. The method of claim 1 , wherein the first dielectric material includes silicon nitride.
9. The method of claim 1 , wherein forming the source/drain contact within the interlevel dielectric layer further includes forming a contact trench in the interlevel dielectric layer and depositing a conductive material in the contract trench.
10. The method of claim 1 , further comprising planarizing the source/drain contract.
11. The method of claim 1 , wherein removing the interlevel dielectric layer includes etching the interlevel dielectric layer.
12. The method of claim 11 , wherein etching the interlevel dielectric layer includes a wet etching process.
13. An apparatus comprising:
a source/drain;
a gate;
a trench contact disposed on the source/drain;
a source/drain contact in contact with the trench contact;
a gate contact in contact with the gate;
a dielectric liner of a first dielectric material deposited upon a top of the gate, the trench contact and the S/D contact, the first dielectric material of the dielectric liner forming an air spacer between the gate and the trench contact.
14. The apparatus of claim 13 , wherein the first dielectric material includes a non-conformal dielectric material.
15. The apparatus of claim 13 , wherein the first dielectric material includes silicon nitride.
16. The apparatus of claim 13 , further comprising:
a second dielectric material deposited upon the dielectric liner.
17. The apparatus of claim 16 , wherein the second dielectric material includes an oxide.
18. The apparatus of claim 16 , wherein the second dielectric material includes a low dielectric constant (low-K) material.
19. A computer usable program product comprising one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising:
program instructions to receive a semiconductor structure, the semiconductor structure including a source/drain, a gate, and a spacer disposed between the source/drain and the gate, the semiconductor structure further including a trench contact disposed on the source/drain and a self-aligned cap disposed on the gate, the semiconductor structure further including an interlevel dielectric layer disposed on the spacer, self-aligned cap, and trench contact;
program instructions to form a source/drain contact within the interlevel dielectric layer in contact with the trench contact;
program instructions to form a gate contact within the interlevel dielectric layer in contact with the gate;
program instructions to remove the interlevel dielectric layer from the spacer, self-aligned cap, and source/drain contact;
program instructions to selectively etch the self-aligned cap and the spacer; and
program instructions to deposit a dielectric liner of a first dielectric material upon a top of the gate, the trench contact and the S/D contact, the first dielectric material of the dielectric liner pinching off a gap between the gate and the trench contact to form an air spacer therebetween.
20. The computer usable program product of claim 19 , the stored program instructions further comprising:
program instructions to deposit a second dielectric material upon the dielectric liner.