IP Library Granted Patent US 9,397,152
Granted Patent B2
US 9,397,152 · App. 14/851,345 · Granted Jul 19, 2016

Multilayer MIM capacitor

Inventors: Kangguo Cheng (Schenectady, NY); Joseph Ervin (Wappingers Falls, NY); Chengwen Pei (Danbury, CT); Ravi M. Todi (San Diego, CA); Geng Wang (Stormville, NY)
Assignee: International Business Machines Corporation
H01L28/40
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Quick Facts
Patent No.
US 9,397,152
App. No.
14/851,345
Granted
Jul 19, 2016
Kind
B2
Abstract

A semiconductor capacitor and method of fabrication is disclosed. A MIM stack, having alternating first-type and second-type metal layers (each separated by dielectric) is formed in a deep cavity. The entire stack can be planarized, and then patterned to expose a first area, and selectively etched to recess all first metal layers within the first area. A second selective etch is performed to recess all second metal layers within a second area. The etched recesses can be backfilled with dielectric. Separate electrodes can be formed; a first electrode formed in said first area and contacting all of said second-type metal layers and none of said first-type metal layers, and a second electrode formed in said second area and contacting all of said first-type metal layers and none of said second-type metal layers.

Claims (34)

1. A method to form a deep-trench capacitor comprising:

providing substrate having a stack of metal layers in a cavity, said stack comprising first-type metal layers and second-type metal layers, wherein each adjacent pair of said stack comprises one first-type metal layer and one second-type metal layer, said stack further comprising an insulating layer between said adjacent pairs;

exposing a cross section of said stack;

etching said first-type metal layers within a first area of said cross section while not appreciably etching said second-type metal layers, wherein said etching said first-type metal layers creates a first recess;

etching said second-type metal layers within a second area of said cross section while not appreciably etching said first-type metal layers, wherein said etching said second-type metal layers creates a second recess;

filling said first recess and said second recess with a dielectric; and

connecting said first-type metal layers to said second-type metal layers by forming a conductive structure in contact with second-type metal layers within said first area and in contact with first-type metal layers within said second area.

2. The method of claim 1 , further comprising:

etching said conductive structure to form a first electrode fully within said first area and a second electrode fully within said second area.

3. The method of claim 2 , wherein said etching said conductive structure is by reactive ion etch.

4. The method of claim 1 , wherein either of said etching steps comprises applying an etchant of hydrofluoric acid.

5. The method of claim 1 , wherein either of said etching steps comprises applying an etchant of hydrochloric acid.

6. The method of claim 1 , further comprising:

depositing at least one metal layer of said stack in said cavity by atomic layer deposition.

7. The method of claim 1 , further comprising:

depositing at least one of said insulating layer by PECVD or by atomic layer deposition.

8. The method of claim 1 , further comprising:

forming an insulating layer between said stack and said cavity by thermal processing.

9. A method to form a deep-trench capacitor comprising:

providing substrate having a stack of metal layers in a cavity, said stack comprising first-type metal layers and second-type metal layers, wherein each adjacent pair of said stack comprises one first-type metal layer and one second-type metal layer, said stack further comprising an insulating layer between said adjacent pairs;

exposing a cross section of said stack;

etching said first-type metal layers within a first area of said cross section while not appreciably etching said second-type metal layers, wherein said etching said first-type metal layers creates a first recess;

etching said second-type metal layers within a second area of said cross section while not appreciably etching said first-type metal layers, wherein said etching said second-type metal layers creates a second recess;

filling said first recess and said second recess with a dielectric;

covering said cross section with a conductive layer; and

etching said conductive layer to form a first electrode fully within said first area and a second electrode fully within said second area.

10. The method of claim 9 , wherein either of said etching steps comprises applying an etchant of hydrofluoric acid.

11. The method of claim 9 , wherein either of said etching steps comprises applying an etchant of hydrochloric acid.

12. The method of claim 9 , further comprising:

depositing at least one metal layer of said stack in said cavity by atomic layer deposition.

13. The method of claim 9 , further comprising:

depositing at least one of said insulating layer by PECVD or by atomic layer deposition.

14. The method of claim 9 , further comprising:

forming an insulating layer between said stack and said cavity by thermal processing.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052561/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2015
From: CHENG, KANGGUO; ERVIN, JOSEPH; PEI, CHENGWEN; TODI, RAVI M.; WANG, GENG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036556/0476 →
Continuity (2)
Division 14532281 · Nov 4, 2014
Related Publication 20160126305A1 · May 5, 2016