Inducing stress in CMOS device

1. A method of forming a semiconductor device, the method comprising:

providing a complimentary metal oxide semiconductor (CMOS) device including:

a silicon substrate layer;

a silicon dioxide layer thereover; and

an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer;

depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench;

depositing an oxide layer over the nitride stress liner;

placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer;

removing the silicon substrate layer;

etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recessed source/drain trench; and

forming a contact in the opening.

2. The method according to claim 1 , wherein the forming of the contact includes depositing a silicide in the opening.

3. The method of claim 2 , wherein the forming of the contact further includes depositing a contact metal over the silicide.

4. The method according to claim 1 , wherein the etching of the silicon dioxide layer is performed by reactive ion etching.

5. The method of claim 1 , further comprising planarizing the oxide layer.

6. The method of claim 1 , wherein the CMOS device further includes a first spacer abutting the NFET gate and a second spacer abutting the PFET gate, and further comprising:

removing the first spacer to form the first source/drain trench and removing the second spacer to form the second source/drain trench.

7. The method of claim 1 , further comprising: depositing a metal liner over the nitride stress liner before the depositing of the oxide layer.