Method of charge controlled patterning during reactive ion etching
A plasma processing apparatus for reactive ion etching a wafer includes a wafer chuck within a chamber and an electrode for creating a plasma within the chamber above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p− layer and an n+ layer. Both p− and n+ layers have exposed peripheral edges. Also provided is an anode comprising the plasma, a cathode comprising the wafer chuck, and a gate comprising the peripheral edge of the n+ layer. A coating layer is formed on a portion of the peripheral edge of the n+ layer. The coating layer reduces charge flow to a portion of the semiconductor wafer below the coating layer.
1. A plasma processing system comprising:
a plasma processing apparatus comprising:
a wafer chuck within a chamber;
an electrode for creating a plasma within the chamber above the wafer chuck;
an anode comprising the plasma; and
a cathode comprising the wafer chuck;
a semiconductor wafer between the wafer chuck and the electrode, the semiconductor wafer having a p− layer and, above the p− layer, a n+ layer, the p− layer and the n+ layer each having a peripheral edge;
a gate comprising the peripheral edge of the n+ layer; and
a coating layer on a portion of the peripheral edge of the n+ layer;
wherein the coating layer reduces charge flow to a portion of the semiconductor wafer below the coating layer.
2. The system of claim 1 , further comprising a major portion of the n+ layer free of the coating layer.
3. The system of claim 1 , wherein the coating layer is an electrical non-conductor.
4. The system of claim 3 , wherein the coating layer is a polymer.
5. The system of claim 1 , wherein the coating layer is a resist.
6. The system of claim 1 , further comprising a bevel between a surface of the n+ layer and the n+ layer peripheral edge, and wherein the coating layer extends along the bevel.
7. The system of claim 6 , wherein the coating layer extends along a portion of the surface of the n+ layer adjacent to the n+ layer peripheral edge.
8. The system of claim 6 , wherein the coating layer extends along a portion of a peripheral edge of the semiconductor wafer in contact with the wafer chuck.
9. A plasma processing system comprising:
a plasma processing apparatus comprising:
a wafer chuck within a chamber;
an electrode for creating a plasma within the chamber above the wafer chuck;
an anode comprising the plasma; and
a cathode comprising the wafer chuck;
a semiconductor wafer between the wafer chuck and the electrode, the semiconductor wafer having a p− layer and, above the p− layer, a n+ layer, the p− layer and the n+ layer each having a peripheral edge;
a gate comprising the peripheral edge of the n+ layer; and
a dopant formed in a portion of the peripheral edge of the n+ layer;
wherein the dopant reduces charge flow to a portion of the semiconductor wafer adjacent to the portion of the peripheral edge of the n+ layer.
10. The system of claim 9 , wherein a major portion of the n+ layer is free of the dopant.
11. The system of claim 9 , wherein the dopant is an n-type dopant.
12. The system of claim 9 , wherein the dopant is a p-type dopant.
13. The system of claim 9 , wherein the dopant is implanted along a portion of a surface of the n+ layer adjacent to the n+ layer peripheral edge.
14. The system of claim 9 , wherein the dopant is implanted along a portion of a peripheral edge of the semiconductor wafer in contact with the wafer chuck.
15. The system of claim 9 , further comprising a bevel between a surface of the n+ layer and the n+ layer peripheral edge, and wherein the dopant is formed in the bevel.
16. A plasma processing system comprising:
a plasma processing apparatus comprising:
a wafer chuck within a chamber;
an electrode for creating a plasma within the chamber above the wafer chuck;
an anode comprising the plasma; and
a cathode comprising the wafer chuck;
a semiconductor wafer between the wafer chuck and the electrode, the semiconductor wafer having a p− layer and, above the p− layer, a n+ layer, the p− layer and the n+ layer each having a peripheral edge;
a gate comprising the peripheral edge of the n+ layer; and
a dopant formed in a portion of the peripheral edge of the n+ layer;
wherein a conductivity between the p− layer and the wafer chuck varies as a function of a radial distance from a center of the wafer chuck to reduce charge flow to a portion of the semiconductor wafer adjacent to the n+ layer peripheral edge.
17. The system of claim 16 , wherein the conductivity of the wafer chuck varies as a function of the radial distance from the center of the wafer chuck.
18. The system of claim 17 , wherein the conductivity increases towards the center and decreases towards an edge of the wafer chuck.
19. The system of claim 17 , wherein the conductivity of a portion of the wafer chuck adjacent to a peripheral edge of the semiconductor wafer is less than the conductivity of a second portion of the wafer chuck.
20. The system of claim 16 , wherein a degree of electrical contact between the wafer chuck and the semiconductor wafer varies as a function of the radial distance from the center of the wafer chuck.