Signal path of a multiple-patterned semiconductor device
A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.
1. A semiconductor device, comprising:
a signal conductor layer comprising:
a first signal track having a design width on the signal conductor layer defined by a first mask and processed to a first physical width;
a second signal track having the design width on the signal conductor layer defined by a second mask and processed to a second physical width, wherein the first signal track is adjacent to the second signal track and physical widths defined by a single mask more closely track than physical widths defined by separate masks; and
a repeater structure to achieve a timing tolerance standard adapted to repower a first signal on a first conductor in the first signal track and transfer the first signal to a second conductor in the second signal track, and to repower a second signal on a third conductor in the second signal track and transfer the second signal to a fourth conductor in the first signal track.
2. The semiconductor device of claim 1 , wherein the repeater structure is adapted to transfer a signal to a conductor in a signal track in a different signal conductor layer.
3. The semiconductor device of claim 1 , wherein the timing tolerance standard includes a difference from an amount of time for a signal path to carry a signal a distance.
4. The semiconductor device of claim 1 , wherein the repeater structure is adapted to alternate the signal between the signal tracks to achieve the timing tolerance standard.
5. A semiconductor device, comprising:
a layer having a first signal track having a design width created by a first mask and processed to a first physical width and a second signal track having the design width created by a second mask and processed to a second physical width, wherein physical widths defined by a single mask more closely track than physical widths defined by separate masks; and
a switch adapted to criss-cross a first signal from the first signal track to the second signal track and adapted to criss-cross a second signal from the second signal track to the first signal track, wherein the second signal track is an odd number of signal tracks away from the first signal track.
6. The semiconductor device of claim 5 , wherein the switch includes a buffer circuit to repower a signal.
7. The semiconductor device of claim 5 , wherein the switch is adapted to alternate the signal between the first signal track and the second signal track to achieve a timing tolerance standard.
8. The semiconductor device of claim 7 , wherein the timing tolerance standard includes a difference in a transmission time between the first and second signals.
9. A design structure tangibly embodied in a non-transitory machine-readable storage medium used in a design process of a semiconductor device, the design structure having elements that, when processed in a semiconductor manufacturing facility, produce a semiconductor device that comprises:
a signal conductor layer comprising:
a first signal track having a design width on the signal conductor layer defined by a first mask and processed to a first physical width;
a second signal track having the design width on the signal conductor layer defined by a second mask and processed to a second physical width, wherein the first signal track is adjacent to the second signal track and physical widths defined by a single mask more closely track than physical widths defined by separate masks; and
a repeater structure to achieve a timing tolerance standard adapted to repower a first signal on a first conductor in the first signal track and transfer the first signal to a second conductor in the second signal track, and to repower a second signal on a third conductor in the second signal track and transfer the second signal to a fourth conductor in the first signal track.
10. The design structure of claim 9 , wherein the design structure comprises a netlist, which describes the semiconductor device.
11. The design structure of claim 9 , wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.
12. The design structure of claim 9 , wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.