Preventing strained fin relaxation
A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.
1. A semiconductor structure comprising:
a first strained fin portion and a second strained fin portion upon a multilayered substrate;
a pair of inactive inner gate structures upon the multilayered substrate and upon respective strained fin portions, wherein the first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures; and
spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces.
2. The semiconductor structure of claim 1 , wherein the spacer formed upon the first strained fin portion and the second strained fin portion end surfaces limit relaxation of the first strained fin portion and the second strained fin portion.
3. The semiconductor structure of claim 1 , wherein the spacer formed upon the first strained fin portion and the second strained fin portion end surfaces limits shorting between the first strained fin portion and the second strained fin portion.
4. The semiconductor structure of claim 1 , further comprising:
one or more outer gate structures upon the strained multilayered substrate and upon the strained fin outside the pair of inactive inner gate structures; and
spacers upon sidewall surfaces of the one or more outer gate structures.
5. The semiconductor structure claim 1 , wherein the pair of the inactive inner gate structures are electrically inactive.
6. The semiconductor structure of claim 4 , wherein the one or more outer gate structures are electrically active.
7. The semiconductor structure of claim 4 , wherein the fin portion ends are tucked in from respective inner sidewall surfaces of the inactive inner gate structures, and wherein the spacer formed upon the exposed fin portion ends prevent epi nodule formation.
8. The semiconductor structure of claim 4 , wherein the one or more outer gate structure comprise a width equal to respective widths of the pair of the inactive inner gate structures.
9. The semiconductor structure of claim 4 , wherein the one or more outer gate structure comprise a width greater to respective widths of the pair of the inactive inner gate structures.
10. The semiconductor structure of claim 1 , wherein the strained multilayered substrate is a SiGe on insulator (SGOI) substrate.