Semiconductor-on-insulator (SOI) structures with local heat dissipater(s) and methods
Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.
1. A semiconductor-on-insulator (SOI) structure comprising:
a semiconductor substrate;
an insulator layer on and immediately adjacent to said semiconductor substrate;
a semiconductor layer on and immediately adjacent to said insulator layer, said semiconductor layer comprising an active region of a semiconductor device; and
a local heat dissipater comprising:
an opening extending vertically through said insulator layer from said semiconductor layer to said semiconductor substrate, said opening being aligned below said active region; and
a fill material filling said opening so as to be immediately adjacent to said active region in said semiconductor layer and further so as to be immediately adjacent to said semiconductor substrate,
said fill material comprising an electrically insulative material such that said fill material and said insulator layer electrically isolate said semiconductor layer from said semiconductor substrate, and
said fill material being more thermally conductive than said insulator layer such that said fill material dissipates heat from said active region into said semiconductor substrate.
2. The semiconductor-on-insulator (SOI) structure of claim 1 , said fill material further being less electrically conductive than said semiconductor substrate and more thermally conductive and less electrically conductive than said semiconductor layer.
3. The semiconductor-on-insulator (SOI) structure of claim 1 , said semiconductor device comprising a field effect transistor and said heat dissipater being any one of aligned below a source/drain extension within said active region, aligned below a source/drain within said active region, and aligned below a channel within said active region.
4. The semiconductor-on-insulator (SOI) structure of claim 1 , further comprising a shallow trench isolation region above said insulator layer and positioned laterally around said active region,
said semiconductor device comprising a field effect transistor,
said active region comprising a channel positioned laterally between source/drain regions, and
said opening further extending through said shallow trench isolation region and said insulator layer such that said heat dissipater is parallel to and positioned laterally adjacent to said channel within said active region.
5. The semiconductor-on-insulator (SOI) structure of claim 1 , said opening having an essentially uniform width.
6. The semiconductor-on-insulator (SOI) structure of claim 1 , said opening having a lower portion and an upper portion, said lower portion being wider than said lower portion.
7. A method of forming a semiconductor-on-insulator (SOI) structure, said method comprising:
forming an insulator layer on and immediately adjacent to a semiconductor substrate;
forming a local heat dissipater in said insulator layer, said forming of said local heat dissipater comprising:
forming an opening extending vertically through said insulator layer to said semiconductor substrate;
depositing a fill material in said opening such that said fill material is immediately adjacent to said semiconductor substrate;
after said forming of said local heat dissipater, forming a semiconductor layer on and immediately adjacent to said insulator layer and said fill material within said opening; and
forming a semiconductor device having an active region in said semiconductor layer, said active region being aligned above and immediately adjacent to said local heat dissipater,
said fill material comprising an electrically insulative material such that said fill material and said insulator layer electrically isolate said semiconductor layer from said semiconductor substrate, and
said fill material further being more thermally conductive than said insulator layer such that said fill material dissipates heat from said active region into said semiconductor substrate.
8. The method of claim 7 , said fill material further being less electrically conductive than said semiconductor substrate and more thermally conductive and less electrically conductive than said semiconductor layer.
9. The method of claim 7 ,
said semiconductor device comprising a field effect transistor, and
said forming of said semiconductor device and said forming of said local heat dissipater being performed such that said local heat dissipater is any one of aligned below a source/drain extension within said active region, aligned below a source/drain within said active region, and aligned below a channel within said active region.
10. The method of claim 7 , said forming of said opening being performed such that said opening has an essentially uniform width.
11. The method of claim 7 , said forming of said opening being performed such that said opening has a lower portion and an upper portion, said lower portion being wider than said lower portion.
12. A method of forming a semiconductor-on-insulator (SOI) structure, said method comprising:
providing a semiconductor-on-insulator wafer comprising:
a semiconductor substrate;
an insulator layer on and immediately adjacent to said semiconductor substrate; and
a semiconductor layer on and immediately adjacent to said insulator layer;
forming a local heat dissipater, said forming of said local heat dissipater comprising:
forming an opening extending vertically through said semiconductor layer and said insulator layer to said semiconductor substrate;
depositing a fill material into said opening immediately adjacent to said semiconductor substrate;
etching back said fill material to at least level with a top surface of said insulator layer; and
depositing additional semiconductor material within said opening on said fill material; and
any one of before said forming of said local heat dissipater and after said forming of said local heat dissipater, forming a semiconductor device having an active region in said semiconductor layer such that, within said semiconductor-on-insulator (SOI) structure, said local heat dissipater is aligned below and immediately adjacent to said active region,
said fill material comprising an electrically insulative material such that said fill material and said insulator layer electrically isolate said semiconductor layer and said additional semiconductor material from said semiconductor substrate, and
said fill material further being more thermally conductive than said insulator layer such that said fill material dissipates heat from said active region into said semiconductor substrate.
13. The method of claim 12 , said fill material further being less electrically conductive than said semiconductor substrate and more thermally conductive and less electrically conductive than said semiconductor layer.
14. The method of claim 12 ,
said semiconductor device comprising a field effect transistor, and
said forming of said semiconductor device and said forming of said local heat dissipater being performed such that said local heat dissipater is any one of aligned below a source/drain extension within said active region, aligned below a source/drain within said active region, and aligned below a channel within said active region.
15. The method of claim 12 , said forming of said opening being performed such that said opening has an essentially uniform width.
16. The method of claim 12 , said forming of said opening being performed such that said opening has a lower portion and an upper portion, said lower portion being wider than said lower portion.
17. A method of forming a semiconductor-on-insulator (SOI) structure, said method comprising:
providing a semiconductor-on-insulator wafer comprising:
a semiconductor substrate;
an insulator layer on and immediately adjacent to said semiconductor substrate; and
a semiconductor layer on and immediately adjacent to said insulator layer;
forming a shallow trench isolation region extending vertically through said semiconductor layer to said insulator layer and defining an active region for a semiconductor device within said semiconductor layer;
forming at least one local heat dissipater, said forming of said at least one local heat dissipater comprising:
forming, on opposing sides of said active region, openings extending vertically through said shallow trench isolation region and said insulator layer to said semiconductor substrate; and
depositing a fill material in said openings such that said fill material is immediately adjacent to said semiconductor substrate; and
etching said fill material to a level between a top surface and a bottom surface of said shallow trench isolation region such that at least an upper portion of said fill material in each of said openings is positioned laterally adjacent to said active region,
said fill material comprising an electrically insulative material such that said shallow trench isolation region, said fill material and said insulator layer electrically isolate said semiconductor layer from said semiconductor substrate, and
said fill material further being more thermally conductive than said shallow trench isolation region and said insulator layer such that said fill material dissipates heat from said active region into said semiconductor substrate.
18. The method of claim 17 , said fill material further being less electrically conductive than said semiconductor substrate and more thermally conductive and less electrically conductive than said semiconductor layer.
19. The method of claim 17 ,
said semiconductor device comprising a field effect transistor,
said active region comprising a channel,
said forming of said openings comprising forming said openings through said shallow trench isolation region such that said openings are parallel and adjacent to said channel,
said method further comprising, after said forming of said openings, performing an isotropic etch process to form a cavity below said channel
said depositing of said fill material filling said cavity,
said etching of said fill material comprising etching said fill material to below said level of said top surface of said shallow trench isolation region, and
said method further comprising, after said etching, depositing additional isolation material within said openings on said fill material.
20. The method of claim 17 ,
said semiconductor device comprising a field effect transistor,
said active region comprising a channel,
said forming of said openings comprising forming said openings through said shallow trench isolation region such that said openings are parallel and adjacent to said channel,
said etching of said fill material comprising etching said fill material to below said level of said top surface of said shallow trench isolation region, and
said method further comprising, after said etching, depositing additional isolation material within said openings on said fill material.
21. The method of claim 20 , said forming of said openings being performed such that said openings have an essentially uniform width.
22. The method of claim 20 , said forming of said openings being performed such that said openings have a lower portion and an upper portion, said lower portion being wider than said lower portion.