Backside contact to a final substrate

1. A device structure formed using a silicon-on-insulator substrate, the device structure comprising:

a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer;

a trap-rich layer between a substrate and the buried insulator layer of the silicon on-insulator substrate;

an electrically-conducting connection located in a first trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate, the electrically-conducting connection at least partially comprised of trap-rich material;

a first trench isolation region in the device layer located on a first side of the first trench; and

a second trench isolation region in the device layer located on a second side of the first trench.

2. The device structure of claim 1 , wherein the first trench isolation region, the second trench isolation region and the buried insulator layer electrically isolate a first device layer portion used to form the first switch from a second device layer portion used to form the second switch.

3. The device structure of claim 1 , further comprising:

a second trench extending from the device layer through the buried insulator layer to the trap-rich layer;

a third trench isolation region in the device layer located on a first side of the second trench; and

a fourth trench isolation region in the device layer located on a second side of the second trench;

wherein the buried insulator layer comprises a first surface in contact with the device layer and a second surface.

4. The device structure of claim 3 , wherein the trap-rich layer is on the second surface of the buried insulator layer.

5. The device structure of claim 1 , wherein the electrically-conducting connection is a contact plug comprised of a semiconductor material.

6. The device structure of claim 5 , wherein the semiconductor material is polycrystalline silicon.

7. The device structure of claim 5 , wherein the trench includes a bottom surface and an etch stop at the bottom surface, the etch stop comprised of a dielectric material that etches selective to the semiconductor material of the contact plug.

8. The device structure of claim 7 , wherein the dielectric material is comprised of silicon nitride or silicon dioxide.

9. The device structure of claim 4 , wherein the electrically-conducting connection is fully comprised of the trap-rich material.

10. The device structure of claim 4 , wherein the electrically-conducting connection comprises a portion of the trap-rich layer.

11. A device structure formed using a silicon-on-insulator substrate, the device structure comprising:

a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer;

a trap-rich layer between a substrate and the buried insulator layer of the silicon on-insulator substrate;

a first trench isolation region in the device layer; and

a second trench isolation region in the device layer, wherein the first trench isolation region, the second trench isolation region and the buried insulator layer electrically isolate a first device layer portion used to form the first switch from a second device layer portion used to form the second switch.

12. The device structure of claim 11 , further comprising an electrically-conducting connection located in a first trench extending from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate, wherein the first trench isolation region is located on a first side of the first trench, and the second trench isolation region is located on a second side of the first trench.

13. The device structure of claim 12 , further comprising:

a second trench extending from the device layer through the buried insulator layer to the trap-rich layer;

a third trench isolation region in the device layer located on a first side of the second trench; and

a fourth trench isolation region in the device layer located on a second side of the second trench;

wherein the electrically-conducting connection at least partially comprised of trap-rich material.

14. The device structure of claim 13 , wherein the buried insulator layer comprises a first surface in contact with the device layer and a second surface.

15. The device structure of claim 14 , wherein the rap-rich layer is on the second surface of the buried insulator layer.

16. The device structure of claim 12 , wherein the electrically-conducting connection is a contact plug comprised of a semiconductor material.

17. The device structure of claim 16 , wherein the trench includes a bottom surface and an etch stop at the bottom surface, the etch stop comprised of a dielectric material that etches selective to the semiconductor material of the contact plug.

18. The device structure of claim 17 , wherein the dielectric material is comprised of silicon nitride or silicon dioxide.

19. The device structure of claim 12 , wherein the electrically-conducting connection is fully comprised of the trap-rich material.

20. The device structure of claim 12 , wherein the electrically-conducting connection comprises a portion of the trap-rich layer.