Chip-on-chip structure and methods of manufacture

1. A method, comprising:

placing a powder on a semiconductor substrate;

sintering the powder to form a plurality of pillars directly in contact with the semiconductor substrate;

repeating the placing and sintering steps until the plurality of pillars reach a predetermined height;

forming a solder cap on the plurality of pillars;

removing non-sintered powder by a cleaning process;

joining the semiconductor substrate to a board using the solder cap and a thermal reflow process;

joining a chip to the semiconductor substrate by a reflow process; and

underfilling empty spaces between the chip, the semiconductor substrate and the board, wherein:

the semiconductor substrate is a wafer placed in a chuck and coated with a plurality of layers of the powder, followed by the laser sintering after each coating to form the pillars directly in contact with the wafer;

joining the chip to the wafer between the pillars;

dicing the wafer to form a plurality chips with the pillars;

bonding a chip without the pillars to a substrate of another chip of a plurality of chips between the pillars;

the chip without the pillars including plating of micro-bumps; and

wherein the board is an organic laminate and the organic laminate is bonded to the another chip by the pillars by a reflow of the solder cap at a reflow temperature of about 250° C. to about 260° C.

2. The method of claim 1 , wherein:

the powder is a copper powder;

the solder cap is a solder cap that is formed by a powder deposition followed by a sintering process; and

the sintering is a laser sintering process.

3. The method of claim 2 , wherein the solder cap is reflowed, prior to the joining.

4. The method of claim 1 , further comprising removing any non-sintered powder from the semiconductor substrate, prior to the joining.

5. The method of claim 1 , wherein the predetermined height of the plurality of pillars is greater than 75 μm.

6. The method of claim 5 , wherein the predetermined height of the plurality of pillars is about 500 μm.

7. The method of claim 1 , wherein the plurality of pillars are tapered.

8. The method of claim 1 , wherein the plurality of pillars are shaped as an hourglass.

9. The method of claim 1 , wherein the powder is an insulator material.

10. A method, comprising:

placing a wafer in a chuck and coating the wafer with a plurality of layers of conductive powder, followed by a laser sintering after each coating to form conductive pillars of a predetermined height directly in contact with the wafer;

forming a solder cap, on the conductive pillars;

removing non-sintered powder by a cleaning process;

joining a chip to the wafer between the conductive pillars;

joining the wafer to a board by a bonding process of the solder cap of the conductive pillars to the board;

dicing the wafer to form a plurality chips with the conductive pillars;

bonding the chip without the conductive pillars to a substrate of another chip of the plurality of chips between the conductive pillars;

the chip without the conductive pillars including plating of micro-bumps; and

the chip without the conductive pillars being bonded to the substrate by a reflow process;

wherein the board is an organic laminate and the organic laminate is bonded to the another chip by the conductive pillars by a reflow of the solder cap at a reflow temperature of about 250° C. to about 260° C.

11. The method of claim 10 , wherein the conductive powder is copper and the solder cap is formed by: deposited solder powder, sintering the solder powder and reflowing the sintered solder powder.

12. The method of claim 10 , wherein the joining of the chip to the wafer is by reflow or thermocompression bonding.

13. The method of claim 10 , wherein the predetermined height is greater than 75 μm.

14. The method of claim 13 , wherein the predetermined height is approximately 500 um.

15. The method of claim 10 , further comprising underfilling spaces between the chip, wafer and board.

16. The method of claim 10 , wherein the conductive pillars are shaped as one of (i) cones with its bases being wider in diameter than its end at the solder cap, and (ii) hourglasses.

17. The method of claim 10 , wherein the joining the wafer to the board is provided by a reflow process.