Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy
A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.
1. A semiconductor structure comprising:
at least one semiconductor fin extending upwards from a pedestal portion of a base semiconductor substrate;
a bottom source/drain structure located on the base semiconductor substrate and located adjacent the pedestal portion, wherein the bottom source/drain structure includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate, and wherein the pedestal portion contains the first dopant species, and wherein the doped semiconductor buffer layer has a topmost surface that is coplanar with a topmost surface of the epitaxial doped semiconductor layer;
a gate structure located above the bottom source/drain structure and on each side of the at least one semiconductor fin; and
a top source/drain structure located on a topmost surface of the at least one semiconductor fin.
2. The semiconductor structure of claim 1 , wherein the pedestal portion has a width that is greater than a width of the at least one semiconductor fin.
3. The semiconductor structure of claim 1 , wherein the gate structure comprises a gate dielectric material layer and a gate conductor, wherein the gate dielectric material layer directly contacts sidewall surfaces of the at least one semiconductor fin.
4. The semiconductor structure of claim 3 , wherein the gate structure further comprises a work function metal layer located between the gate dielectric material layer and the gate conductor.
5. The semiconductor structure of claim 1 , further comprising a bottom spacer located between the gate structure and the bottom source/drain structure, wherein the bottom spacer contacts a lower portion of the least one semiconductor fin.
6. The semiconductor structure of claim 5 , further comprising a top spacer located on a topmost surface of the gate structure and contacting an upper portion of the least one semiconductor fin.
7. The semiconductor structure of claim 1 , wherein the first dopant species has a size that is smaller than a size of the second dopant species.
8. The semiconductor structure of claim 7 , wherein the doped semiconductor buffer layer comprises boron doped silicon or boron doped silicon germanium.
9. The semiconductor structure of claim 8 , wherein the epitaxial doped semiconductor layer comprises gallium doped germanium, gallium doped silicon germanium, indium doped germanium or indium doped silicon germanium.