Directly forming SiGe fins on oxide
Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure. A silicon germanium alloy fin is formed on opposing sidewalls of each semiconductor mandrel structure that is present in a pFET device region of the semiconductor substrate and directly on a surface of each first oxide isolation structure. Each semiconductor mandrel structure is removed and a second oxide isolation structure is formed between each first oxide isolation structure and extending beneath a bottommost surface of each first oxide isolation structure.
1. A semiconductor structure comprising:
a plurality of silicon germanium alloy fins located within a pFET device region of a semiconductor substrate, wherein each silicon germanium alloy fin is located directly on a first oxide isolation structure, and one sidewall surface of each silicon germanium alloy fin is vertically aligned to a sidewall edge of one of said first oxide isolation structures, and wherein each first oxide isolation structure located entirely within said pFET device region contains a pair of spaced apart silicon germanium alloy fins; and
a second oxide isolation structure located between each of said first oxide isolation structures, wherein each of said second oxide isolation structures has a depth that is deeper than a depth of said first oxide isolation structures.
2. The semiconductor structure of claim 1 , wherein each of said second oxide isolation structures has a topmost surface that is coplanar with a topmost surface of each of said first oxide isolation structures.
3. The semiconductor structure of claim 1 , further comprising a functional gate structure straddling over each silicon germanium alloy fin.
4. The semiconductor structure of claim 1 , further comprising a plurality of n-channel semiconductor fins located within an nFET device region of said semiconductor substrate.
5. The semiconductor structure of claim 4 , wherein each n-channel semiconductor material fin is located directly on a first oxide isolation structure located in said nFET device region, wherein one sidewall surface of each n-channel semiconductor material fin is vertically aligned to a sidewall edge of one of said first oxide isolation structures in said nFET device region.
6. The semiconductor structure of claim 5 , further comprising a second oxide isolation structure in said nFET device region and located between each of said first oxide isolation structures in said nFET device region.
7. The semiconductor structure of claim 6 , wherein each of said second oxide isolation structures in said nFET device region has a depth that is deeper than a depth of first oxide isolation structures in said nFET device region.
8. The semiconductor structure of claim 4 , wherein each of said n-channel semiconductor material fins comprises germanium.
9. The semiconductor structure of claim 4 , wherein each of said n-channel semiconductor material fins comprises a III-V compound semiconductor.
10. The semiconductor structure of claim 4 , further comprising a functional gate structure straddling over each n-channel semiconductor material fin.
11. The semiconductor structure of claim 4 , wherein each of said n-channel semiconductor material fins has a same height as that of each silicon germanium alloy fin.
12. The semiconductor structure of claim 4 , wherein each of said n-channel semiconductor material fins has a different height as that of each silicon germanium alloy fin.
13. The semiconductor structure of claim 4 , wherein each of said n-channel semiconductor material fins has a same width as that of each silicon germanium alloy fin.
14. The semiconductor structure of claim 4 , wherein each of said n-channel semiconductor material fins has a different width as that of each silicon germanium alloy fin.
15. The semiconductor structure of claim 1 , wherein each silicon germanium alloy fin is single crystalline.
16. The semiconductor structure of claim 1 , wherein each silicon germanium alloy fin has a germanium content of from 10 atomic percent germanium to 90 atomic percent germanium.
17. The semiconductor structure of claim 1 , wherein each second oxide isolation structure extends below a topmost surface of said semiconductor substrate.
18. A semiconductor structure comprising:
a plurality of silicon germanium alloy fins located within a pFET device region of a semiconductor substrate, wherein each silicon germanium alloy fin is located directly on a first oxide isolation structure, and one sidewall surface of each silicon germanium alloy fin is vertically aligned to a sidewall edge of one of said first oxide isolation structures, and wherein each first oxide isolation structure located entirely within said pFET device region contains a pair of spaced apart silicon germanium alloy fins;
a second oxide isolation structure located between each of said first oxide isolation structures present in said pFET device region, wherein each of said second oxide isolation structures has a depth that is deeper than a depth of said first oxide isolation structures;
a plurality of n-channel semiconductor fins located within an nFET device region of said semiconductor substrate, wherein each n-channel semiconductor material fin is located directly on a first oxide isolation structure located in said nFET device region, wherein one sidewall surface of each n-channel semiconductor material fin is vertically aligned to a sidewall edge of one of said first oxide isolation structures in said nFET device region; and
a second oxide isolation structure in said nFET device region and located between each of said first oxide isolation structures in said nFET device region, wherein a first oxide isolation structure located at the boundary between said pFET device region and said nFET device region includes one silicon germanium alloy in said pFET device region and one n-channel semiconductor material fin in said nFET device region.
19. The semiconductor structure of claim 18 , wherein each of said second oxide isolation structures in said pFET and nFET device regions has a topmost surface that is coplanar with a topmost surface of each of said first oxide isolation structures in said pFET and nFET device regions.