Backside contact to a final substrate
A device structure is formed using a silicon-on-insulator substrate. The device structure includes a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer. An electrically-conducting connection is located in a first trench extending from the device layer through the buried insulator layer to a trap-rich layer such that the electrically-conducting connection is coupled with a substrate.
1. A device structure formed using a silicon-on-insulator substrate, the device structure comprising:
a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer, wherein the buried insulator layer comprises a first surface in contact with the device layer and a second surface;
a first trench including an electrically-conducting connection, wherein the first trench extends from the device layer through the buried insulator layer to a trap-rich layer that is disposed on a substrate and the buried insulator layer of the silicon on-insulator substrate such that the electrically-conducting connection is coupled with the substrate; and
a second trench extending from the device layer through the buried insulator layer to the trap-rich layer.
2. The device structure of claim 1 , wherein the electrically-conducting connection is at least partially comprised of trap-rich material.
3. The device structure of claim 2 , further comprising:
a first trench isolation region in the device layer located on a first side of the first trench; and
a second trench isolation region in the device layer located on a second side of the first trench.
4. The device structure of claim 3 , wherein the first trench isolation region, the second trench isolation region and the buried insulator layer electrically isolate a first device layer portion used to form the first switch from a second device layer portion used to form the second switch.
5. The device structure of claim 3 , further comprising:
a third trench isolation region in the device layer located on a first side of the second trench; and
a fourth trench isolation region in the device layer located on a second side of the second trench.
6. The device structure of claim 5 , wherein:
the trap-rich layer is on the second surface of the buried insulator layer;
the electrically-conducting connection is a contact plug comprised of a semiconductor material;
the semiconductor material is polycrystalline silicon.
7. The device structure of claim 6 , wherein:
the first trench includes a bottom surface and an etch stop at the bottom surface, the etch stop comprised of a dielectric material that etches selective to the semiconductor material of the contact plug; and
the dielectric material is comprised of silicon nitride or silicon dioxide.
8. The device structure of claim 6 , wherein the electrically-conducting connection is fully comprised of the trap-rich material.
9. The device structure of claim 6 , wherein the electrically-conducting connection comprises a portion of the trap-rich layer.
10. A device structure formed using a silicon-on-insulator substrate, the device structure comprising:
a first switch and a second switch that are formed within a device layer of the silicon-on-insulator substrate and between a buried insulator layer of the silicon on-insulator substrate and a dielectric layer disposed above and coupled to the device layer, wherein the buried insulator layer comprises a first surface in contact with the device layer and a second surface;
a trap-rich layer disposed between a substrate and the buried insulator layer of the silicon on-insulator substrate;
a first trench including an electrically-conducting connection, the first trench extends from the device layer through the buried insulator layer to the trap-rich layer such that the electrically-conducting connection is coupled with the substrate; and
a second trench extending from the device layer through the buried insulator layer to the trap-rich layer.
11. The device structure of claim 10 , further comprising:
a first trench isolation region in the device layer; and
a second trench isolation region in the device layer, wherein the first trench isolation region, the second trench isolation region and the buried insulator layer electrically isolate a first device layer portion used to form the first switch from a second device layer portion used to form the second switch.
12. The device structure of claim 11 , wherein the first trench isolation region is located on a first side of the first trench, and the second trench isolation region is located on a second side of the first trench.
13. The device structure of claim 12 , further comprising:
a third trench isolation region in the device layer located on a first side of the second trench; and
a fourth trench isolation region in the device layer located on a second side of the second trench;
wherein the electrically-conducting connection at least partially comprised of trap-rich material.
14. The device structure of claim 13 , wherein the trap-rich layer is on the second surface of the buried insulator layer.
15. The device structure of claim 13 , wherein the electrically-conducting connection is a contact plug comprised of a semiconductor material.
16. The device structure of claim 15 , wherein the first trench includes a bottom surface and an etch stop at the bottom surface, the etch stop comprised of a dielectric material that etches selective to the semiconductor material of the contact plug.
17. The device structure of claim 16 , wherein the dielectric material is comprised of silicon nitride or silicon dioxide.
18. The device structure of claim 12 , wherein the electrically-conducting connection is one of fully comprised of the trap-rich material or comprises a portion of the trap-rich layer.