High density programmable e-fuse co-integrated with vertical FETs
A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
1. A semiconductor device, comprising:
a doped portion of a substrate, wherein the doped portion includes a bottom source/drain region in a transistor region and a bottom cathode/anode region in a fuse region;
a vertical transistor, including:
a first fin formed on the bottom source/drain region in the transistor region and forming a vertical channel for the vertical transistor; and
an electrical fuse co-integrated with the vertical transistor, including:
a vertical silicided link formed from an intermediary portion of a second fin on the bottom cathode/anode region in the fuse region, the intermediary portion disposed above and distinct from the bottom cathode/anode region included in the doped portion.
2. The device of claim 1 , wherein the bottom source/drain region in the transistor region and the bottom cathode/anode region in the fuse region are separated by a shallow trench isolation region.
3. The device of claim 1 , further comprising a gate structure formed on an intermediary portion of the first fin in the transistor region.
4. The device of claim 1 , further comprising a top source/drain region grown on a thinned portion of the first fin.
5. The device as recited in claim 4 , wherein the intermediary portion of the first fin is between the thinned portion and the bottom source/drain region.
6. The device as recited in claim 4 , wherein the top source/drain region has a crystal orientation that is the same as a crystal orientation of the thinned portion of the first fin.
7. The device of claim 1 , further comprising a top cathode/anode region coupled to the link in the fuse region.
8. The device as recited in claim 1 , wherein the channel formed by the first fin and the link formed by the second fin are of about a same height.
9. The device as recited in claim 1 , further comprising:
a dielectric fill formed over the vertical transistor and the electrical fuse and having contacts connected to the bottom source/drain region and the bottom cathode/anode region.
10. The device as recited in claim 1 , further comprising;
a gate structure including a gate dielectric and
a vertically disposed gate conductor; and a gate contact is configured to land on the gate conductor.
11. The device as recited in claim 1 , wherein the doped portion of the substrate includes a doped layer formed on a counter doped layer.
12. The device as recited in claim 1 , wherein the vertical transistor and the electrical fuse are formed within an interlevel dielectric (ILD).
13. A semiconductor device, comprising:
a doped portion of a substrate, wherein the doped portion is separated by a shallow trench isolation region to form a bottom source/drain region in a transistor region and bottom cathode/anode region in a fuse region;
a vertical transistor, including:
a first fin having a bottom portion formed on the bottom source/drain region in the transistor region and forming a vertical channel for the vertical transistor;
a top source/drain region grown on a narrower top portion of the first fin; and
an electrical fuse co-integrated with the vertical transistor, including:
a vertical silicided link formed from an intermediary portion of a second fin disposed on the bottom cathode/anode region in the fuse region in the doped portion of the substrate.
14. The device as recited in claim 13 , wherein the channel formed by the first fin and the link formed by the second fin have an equivalent height.
15. The device as recited in claim 13 , further comprising:
a dielectric fill formed over the vertical transistor and the electrical fuse and having contacts connected to the bottom source/drain region and the bottom cathode/anode region.
16. The device as recited in claim 13 , further comprising a gate structure formed on an intermediary portion of the first fin in the transistor region and wherein the gate structure includes a gate dielectric and a vertically disposed gate conductor; and a gate contact is configured to land on the gate conductor.
17. The device as recited in claim 13 , wherein the intermediary portion of the first fin is between the thinned portion and the bottom source/drain region in the transistor region.
18. The device as recited in claim 13 , wherein the doped portion of the substrate includes a doped layer formed on a counter doped layer.
19. The device as recited in claim 13 , wherein the top source/drain region has a crystal orientation that is the same as a crystal orientation of the thinned portion of the first fin.
20. The device as recited in claim 13 , wherein the vertical transistor and the electrical fuse are formed within an interlevel dielectric (ILD).