Self-cut sidewall image transfer process
A plurality of mandrels is formed on a silicon substrate. The mandrels are spaced apart at a given pitch, wherein at least one of the plurality of mandrels is formed having a first width, and at least another one of the plurality of mandrels is formed having a second width, and wherein the first width is greater than the second width. At least one structure is formed by removing at least a portion of the plurality of mandrels in a sidewall image transfer process without using a cut mask.
1. A semiconductor structure comprising:
a set of first structures formed on a first region of a silicon substrate, wherein each of the first structures comprises a mandrel having a first hardmask disposed on a top surface thereof, wherein the mandrel has a first width and a first height;
a set of second structures formed on a second region of the silicon substrate, wherein each of the second structures comprises a mandrel having a second hardmask disposed on a top surface thereof and an oxide layer disposed on the hardmask, wherein the mandrel has a second width and a second height;
a set of third structures formed on a third region of the silicon substrate, wherein each of the third structures comprises a mandrel having a third hardmask disposed on a top surface thereof, wherein the mandrel has a third width and a third height;
wherein the set of first structures and the set of third structures are separated by the set of second structures and further wherein the second width is greater than the first width and the third width.
2. The semiconductor structure of claim 1 , wherein the first width and the third width are the same.
3. The semiconductor structure of claim 1 , wherein the second height is greater than the first height and the third height.
4. The semiconductor structure of claim 3 , wherein the first height and the third height are the same.
5. The semiconductor structure of claim 2 , wherein the second height is greater than the first height and the third height.
6. The semiconductor structure of claim 5 , wherein the first height and the third height are the same.
7. The semiconductor structure of claim 1 , further comprising a dielectric layer on the silicon substrate.
8. The semiconductor structure of claim 7 , wherein the dielectric layer is disposed over the set of first structures and the set of third structures and coplanar with the set of second structures.
9. The semiconductor structure of claim 3 , further comprising a dielectric layer on the silicon substrate.
10. The semiconductor structure of claim 9 , wherein the dielectric layer is disposed over the set of first structures and the set of third structures and coplanar with the set of second structures.
11. The semiconductor structure of claim 6 , further comprising a dielectric layer on the silicon substrate.
12. The semiconductor structure of claim 11 , wherein the dielectric layer is disposed over the set of first structures and the set of third structures and coplanar with the set of second structures.