Semiconductor nanowire fabrication
Methods are provided for fabricating semiconductor nanowires on a substrate. A nanowire template is formed on the substrate. The nanowire template defines an elongate tunnel which extends, laterally over the substrate, between an opening in the template and a seed surface. The seed surface is exposed to the tunnel and of an area up to about 2×10 4 nm 2 . The semiconductor nanowire is selectively grown, via said opening, in the template from the seed surface. The area of the seed surface is preferably such that growth of the nanowire proceeds from a single nucleation point on the seed surface. There is also provided a method for fabricating a plurality of semiconductor nanowires on a substrate and a semiconductor nanowire and substrate structure.
1. A method for fabricating a semiconductor nanowire on a substrate, the method comprising:
forming a semiconductor layer on a surface of an insulating layer over a substrate;
patterning the semiconductor layer to form a seed region in the shape of an interior of a nanowire template defining an elongated tunnel which extends laterally over the substrate;
forming a masking layer in contact with the seed region and the insulating layer, the masking layer covering a top surface and opposite sidewalls of the seed region;
opening the masking layer to expose a sidewall of the seed region;
recessing the seed region from the exposed sidewall to form a tunnel, the seed region recessed such that a remaining portion of the seed region provides a seed surface comprising a semiconductor material; and
selectively growing the semiconductor nanowire in the tunnel from the seed surface using metal-organic vapor phase deposition (MOCVD) or migration enhanced epitaxy (MEE);
wherein the seed surface comprises a length and a width that are less than an average diffusion length of the semiconductor nanowire at an operating temperature of the selective growth.
2. The method according to claim 1 , wherein an area of the seed surface is no greater than about 10 4 nm 2 .
3. The method according to claim 2 , wherein the area of the seed surface is such that growth of the nanowire proceeds from a single nucleation point on the seed surface.
4. The method according to claim 1 , wherein the seed surface has a width of up to about 100 nm and a breadth, perpendicular to said width, of up to about 100 nm.
5. The method according to claim 1 , wherein the seed surface occludes one end of the tunnel.
6. The method according to claim 5 , wherein the seed surface is perpendicular to the longitudinal axis of the tunnel.
7. The method according to claim 1 , wherein the seed surface is a monocrystalline semiconductor surface.
8. The method according to claim 1 , wherein the seed surface is a surface of consisting of at least one of: an amorphous semiconductor, a polycrystalline semiconductor, a metal, and a metal-semiconductor alloy.
9. The method according to claim 1 , wherein said elongate tunnel has one or more branches, defined by the template, extending therefrom.
10. The method according to claim 9 , wherein the substrate comprises a semiconductor-on-insulator wafer having a semiconductor layer providing said seed layer.
11. The method according to claim 10 , wherein the seed region comprises at least one of: silicon, germanium and alloys thereof.
12. The method according to claim 1 , wherein the nanowire comprises a compound semiconductor material.
13. A method for fabricating a plurality of semiconductor nanowires on a substrate, the method comprising:
forming a stack comprising two or more semiconductor layers alternating with two or more insulating layers on a surface of a substrate;
patterning the two or more semiconductor layers to form seed regions, each seed region in the shape of an interior of a plurality of nanowire templates defining an elongated tunnel which extends laterally over the substrate;
forming a masking layer on a top surface and opposite sidewalls of a topmost seed region of the stack;
opening the masking layer to expose a sidewall of each of the seed regions;
recessing the seed regions from the exposed sidewalls to form a plurality of tunnels, the seed regions recessed such that remaining portions of the seed regions provide a seed surface comprising a semiconductor material; and
selectively growing the plurality of semiconductor nanowires in the tunnels from the seed surface using metal-organic vapor phase deposition (MOCVD) or migration enhanced epitaxy (MEE);
wherein the nanowire templates are vertically-stacked on the substrate; and
wherein each seed surface comprises a length and a width that are less than an average diffusion length of the semiconductor nanowires at an operating temperature of the selective growth.
14. A structure comprising a semiconductor nanowire and a substrate, the structure comprising:
a nanowire template defining a plurality of vertically stacked, elongated tunnels which extend laterally over the substrate;
a seed region within each of the elongated tunnels, each seed region comprising a seed surface having an area of less than about 2×10 4 nm 2 ; and
a semiconductor nanowire selectively grown in each of the tunnels from the seed surfaces;
wherein each seed surface comprises a length and a width that are less than an average diffusion length of the semiconductor nanowire at an operating temperature of the selective growth.