TRANSISTOR WITH ASYMMETRIC SOURCE/DRAIN OVERLAP
An asymmetric field-effect transistor having different gate-to-source and gate-to-drain overlaps allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. Source and drain regions having different configurations can be formed simultaneously using the same precursor materials.
1 . An asymmetric field-effect transistor device comprising:
a semiconductor substrate including a semiconductor fin comprising a first region, a second region, and a channel region within the semiconductor fin between the first and second regions, the first region including a recess extending vertically within the semiconductor fin, the second region comprising an unrecessed portion of the semiconductor fin;
a gate electrode including a drain side and a source side, the gate electrode being operatively associated with the channel region;
a gate dielectric layer between the gate electrode and the channel region;
a doped, embedded epitaxial source region on the first region of the semiconductor substrate and extending within the recess; and
a doped, cladded epitaxial drain region on the second region of the semiconductor substrate.
2 . (canceled)
3 . The asymmetric field-effect transistor device of claim 1 , wherein the source region extends beneath a portion of the gate dielectric layer and laterally further towards the channel region than the drain region.
4 . The asymmetric field-effect transistor device of claim 3 , wherein the source region, but not the drain region, extends beneath a portion of the gate electrode.
5 . The asymmetric field-effect transistor device of claim 3 , further including:
a source contact electrically connected to the source region;
a drain contact electrically connected to the drain region, and
a plurality of vertical sidewall spacers, each source contact and each drain contact being positioned between a pair of the plurality of vertical sidewall spacers.
6 . The asymmetric field-effect transistor device of claim 5 , wherein the source region includes top surfaces adjoining one of the pairs of the plurality of vertical sidewall spacers.
7 . The asymmetric field-effect transistor device of claim 6 , wherein the drain region includes top surfaces adjoining one of the pairs of the plurality of vertical sidewall spacers.
8 . The asymmetric field-effect transistor device of claim 1 , further including:
a source contact electrically connected to the source region;
a drain contact electrically connected to the drain region, and
a plurality of vertical sidewall spacers, each source contact and each drain contact being positioned between a pair of the plurality of vertical sidewall spacers.
9 . The asymmetric field-effect transistor device of claim 8 , wherein the source region and the drain region both include lateral portions extending beneath one of the pairs of the plurality of the vertical sidewall spacers.
10 . The asymmetric field-effect transistor device of claim 1 , wherein the recess extends between twenty and sixty nanometers within the semiconductor fin.
11 . The asymmetric field-effect transistor device of claim 1 , wherein the semiconductor substrate includes a plurality of parallel semiconductor fins, further including an electrically insulating, shallow trench isolation layer having a top surface between the plurality of parallel semiconductor fins, the doped epitaxial source region, but not the doped epitaxial drain region, extending beneath the top surface of the shallow trench isolation layer.
12 . An asymmetric field-effect transistor structure comprising:
a plurality of parallel semiconductor fins, each of the semiconductor fins including sidewalls and a channel region;
a gate electrode extending across the semiconductor fins, the gate electrode having a first side and a second side and being operatively associated with the channel regions of the semiconductor fins;
a gate dielectric layer between the gate electrode and each of the channel regions;
an electrically insulating, shallow trench isolation layer having a top surface, the semiconductor fins having bottom portions embedded within the shallow trench isolation layer;
a recess extending within each of the semiconductor fins on the first side of the gate electrode, the semiconductor fins including unrecessed portions on the second side of the gate electrode;
a plurality of embedded, epitaxial source regions on the semiconductor fins, each of the epitaxial source regions being doped and extending within one of the recesses and beneath the top surface of the shallow trench isolation layer; and
a plurality of cladded, doped epitaxial drain regions on the sidewalls of the unrecessed portions of the semiconductor fins, none of the doped epitaxial drain regions extending beneath the top surface of the shallow trench isolation layer.
13 . The asymmetric field-effect transistor structure of claim 12 , wherein the doped epitaxial source regions have greater volumes than the doped epitaxial drain regions.
14 . The asymmetric field-effect transistor structure of claim 13 , wherein the doped epitaxial source regions extend beneath portions of the gate dielectric layer.
15 . The asymmetric field-effect transistor structure of claim 14 , wherein the doped epitaxial source regions extend beneath portions of the gate electrode.
16 . The asymmetric field-effect transistor structure of claim 14 , further including:
source contacts electrically connected to the doped epitaxial source regions;
drain contacts electrically connected to the doped epitaxial drain regions, and
a plurality of vertical sidewall spacers, each source contact and each drain contact being positioned between a pair of the plurality of vertical sidewall spacers.
17 . The asymmetric field-effect transistor structure of claim 16 , wherein the doped epitaxial source regions include top surfaces adjoining pairs of the plurality of vertical sidewall spacers.
18 . The asymmetric field-effect transistor structure of claim 16 , wherein the recesses have depths between twenty and sixty nanometers.
19 - 20 . (canceled)
21 . The asymmetric field-effect transistor device of claim 1 , further including doped junctions extending laterally, respectively, from the source region and the drain region, there being a greater overlap between the doped junction extending from the source region and the gate electrode than between the doped junction extending from the drain region and the gate electrode.
22 . The asymmetric field-effect transistor device of claim 21 , wherein the source region has a greater volume than the drain region.