VFET metal gate patterning for vertical transport field effect transistor

1. A method for forming a semiconductor structure, the method comprising:

forming a conformal PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region;

forming a sacrificial layer on the PFET work function metal layer in the PFET region and in the NFET region, wherein a thickness of the sacrificial layer is greater on a horizontal top surface of both the PFET fin and the NFET fin, than a thickness of the sacrificial layer on a vertical side surface of both the PFET fin and the NFET fin;

thinning the sacrificial layer, wherein a remaining portion of the sacrificial layer remains on the horizontal top surface of both the PFET fin and the NFET fin, a remaining portion of the sacrificial layer remains on a vertical side surface of both the PFET fin and the NFET fin, and a portion of a horizontal top surface of an insulator layer is exposed between the PFET fin and the NFET fin; and

patterning an organic planarization layer on the PFET work function metal layer, wherein the organic planarization layer covers the PFET region and partially covers the NFET region.

2. The method according to claim 1 , further comprising:

removing the sacrificial layer in the NFET region, by etching isotropically selective to the organic planarization layer and the PFET work function metal layer in the NFET region;

removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and the insulator layer in the NFET region;

removing the organic planarization layer; and

removing the sacrificial layer.

3. The method according to claim 1 , further comprising:

conformally forming an NFET work function metal layer on the semiconductor structure.

4. The method according to claim 3 , further comprising:

etching the NFET work function metal layer anisotropically to a uniform thickness.

5. The method according to claim 4 , further comprising:

removing the PFET work function metal layer and the NFET work function metal layer along the horizontal top surface of the PFET fin;

removing a portion of the PFET work function metal layer and the NFET work function metal layer along a vertical side surface of the PFET fin;

removing the NFET work function metal layer from the horizontal top surface of the NFET fin; and

removing a portion of the NFET work function metal layer along a portion of a vertical side surface of the NFET fin.

6. The method according to claim 5 , further comprising:

forming a dielectric layer;

forming a PFET bottom source drain contact;

forming a PFET top source drain contact;

forming a gate contact connected to the NFET work function metal layer;

forming an NFET bottom source drain contact; and

forming an NFET top source drain contact.

7. The method according to claim 1 , further comprising:

conformally forming a common metal layer in the PFET region and in the NFET region;

removing a portion of the common metal layer and a portion of the PFET work function metal layer along a vertical side surface of the PFET fin; and

removing a portion of the common metal layer and a portion of the NFET work function metal layer from the horizontal top surface of the NFET fin.

8. The method according to claim 1 , further comprising:

epitaxially growing a PFET bottom source drain on the semiconductor structure, wherein the PFET fin is subsequently formed above the PFET bottom source drain;

epitaxially growing a NFET bottom source drain on the semiconductor structure, wherein the NFET fin is subsequently formed above the NFET bottom source drain;

epitaxially growing a PFET top source drain on a top surface of the PFET fin; and

epitaxially growing a NFET top source drain on a top surface of the NFET fin.

9. A method for forming a semiconductor structure, the method comprising:

forming a conformal PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region;

forming a conformal sacrificial buffer on the PFET work function metal layer in the PFET region and in the NFET region;

forming a conformal cap layer on the sacrificial buffer in the PFET region and in the NFET region;

forming a sacrificial layer on the PFET work function metal layer in the PFET region and in the NFET region, wherein a thickness of the sacrificial layer is greater on a horizontal top surface of both the PFET fin and the NFET fin, than a thickness of the sacrificial layer on a vertical side surface of both the PFET fin and the NFET fin;

thinning the sacrificial layer and removing the cap layer, the sacrificial buffer, and the PFET work function metal layer in an area between the PFET fin and the NFET fin, such that a remaining portion of the sacrificial layer remains on the horizontal top surface of both the PFET fin and the NFET fin, and a remaining portion of the sacrificial layer remains on a vertical side surface of both the PFET fin and the NFET fin, and a portion of a horizontal top surface of an insulator layer is exposed between the PFET fin and the NFET fin; and

patterning an organic planarization layer on the PFET work function metal layer, wherein the organic planarization layer covers the PFET region and partially covers the NFET region.

10. The method according to claim 9 , further comprising:

removing the sacrificial layer in the NFET region, by etching isotropically selective to the organic planarization layer and the cap layer, the sacrificial buffer in the NFET region;

removing the cap layer and in the NFET region, by etching isotropically selective to the organic planarization layer and the insulator layer in the NFET region;

removing the sacrificial buffer in the NFET region, by etching isotropically selective to the organic planarization layer and the PFET work function metal layer in the NFET region;

removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and the insulator layer in the NFET region; and

removing the organic planarization layer.

11. The method according to claim 9 , further comprising:

conformally forming an NFET work function metal layer on the semiconductor structure.

12. The method according to claim 9 , further comprising:

removing the PFET work function metal layer and the NFET work function metal layer along the horizontal top surface of the PFET fin;

removing a portion of the PFET work function metal layer and the NFET work function metal layer along a vertical side surface of the PFET fin;

removing the NFET work function metal layer from the horizontal top surface of the NFET fin; and

removing a portion of the NFET work function metal layer along a portion of a vertical side surface of the NFET fin.

13. The method according to claim 9 , further comprising:

forming a dielectric layer;

forming a PFET bottom source drain contact;

forming a PFET top source drain contact;

forming a gate contact connected to the NFET work function metal layer;

forming an NFET bottom source drain contact; and

forming an NFET top source drain contact.

14. The method according to claim 9 , further comprising:

conformally forming a common metal layer in the PFET region and in the NFET region;

removing a portion of the common metal layer and a portion of the PFET work function metal layer along a vertical side surface of the PFET fin; and

removing a portion of the common metal layer and a portion of the NFET work function metal layer from the horizontal top surface of the NFET fin.

15. The method according to claim 9 , further comprising:

epitaxially growing a PFET bottom source drain on the semiconductor structure, wherein the PFET fin is subsequently formed above the PFET bottom source drain;

epitaxially growing a NFET bottom source drain on the semiconductor structure, wherein the NFET fin is subsequently formed above the NFET bottom source drain;

epitaxially growing a PFET top source drain on a top surface of the PFET fin; and

epitaxially growing a NFET top source drain on a top surface of the NFET fin.

16. A method for forming a semiconductor structure, the method comprising:

forming a conformal PFET work function metal layer on a p-type field effect transistor (PFET) fin in a PFET region and on an n-type field effect transistor (NFET) fin in an NFET region;

forming a conformal sacrificial buffer on the PFET work function metal layer in the PFET region and in the NFET region;

forming a conformal cap layer on the sacrificial buffer in the PFET region and in the NFET region;

forming a conformal sacrificial layer on the PFET work function metal layer in the PFET region and in the NFET region; and

thinning the sacrificial layer, wherein the sacrificial layer from a horizontal top surface of both the PFET fin and the NFET fin, and a remaining portion of the sacrificial layer remains on a vertical side surface of both the PFET fin and the NFET fin with an increasing thickness towards a horizontal top surface of a semiconductor substrate below the PFET region and the NFET region, and a portion of a horizontal top surface of the cap layer is exposed between the PFET fin and the NFET fin.

17. The method according to claim 16 , further comprising:

removing a horizontal portion of the cap layer above the PFET fin and above the NFET fin;

removing a horizontal portion of the sacrificial buffer above the PFET fin and above the NFET fin;

removing a horizontal portion of the PFET work function metal layer above the PFET fin and above the NFET fin; and

patterning an organic planarization layer on the PFET work function metal layer, wherein the organic planarization layer covers the PFET region and partially covers the NFET region.

18. The method according to claim 16 , further comprising:

removing the sacrificial layer in the NFET region, by etching isotropically selective to the organic planarization layer and the cap layer, the sacrificial buffer in the NFET region;

removing the cap layer and in the NFET region, by etching isotropically selective to the organic planarization layer and an insulator layer in the NFET region;

removing the sacrificial buffer in the NFET region, by etching isotropically selective to the organic planarization layer and the PFET work function metal layer in the NFET region;

removing the PFET work function metal layer in the NFET region, by etching isotropically selective to the organic planarization layer and the insulator layer in the NFET region; and

removing the organic planarization layer.

19. The method according to claim 16 , further comprising:

conformally forming an NFET work function metal layer on the semiconductor structure.

20. The method according to claim 16 , further comprising:

epitaxially growing a PFET bottom source drain on the semiconductor structure, wherein the PFET fin is subsequently formed above the PFET bottom source drain;

epitaxially growing a NFET bottom source drain on the semiconductor structure, wherein the NFET fin is subsequently formed above the NFET bottom source drain;

epitaxially growing a PFET top source drain on a top surface of the PFET fin; and

epitaxially growing a NFET top source drain on a top surface of the NFET fin.