BARRIER PLANARIZATION FOR INTERCONNECT METALLIZATION
A method for forming interconnect structures includes forming a barrier material over a dielectric layer having a trench, the barrier layer being disposed on sidewalls and horizontal surfaces of the trench, depositing an interconnect layer over the barrier layer to form an interconnect structure, recessing the interconnect layer down to a surface of the barrier layer using a chemical mechanical planarization process, and planarizing the barrier layer and the interconnect layer using a wet etch process to form a coplanar surface to prevent dishing or divots in the interconnect structure.
1 . A semiconductor device, comprising:
a dielectric layer having at least one trench formed therein;
a barrier material formed on the dielectric layer, the barrier material being disposed on sidewalls and horizontal surfaces of the at least one trench; and
an interconnect layer disposed in the at least one trench to form an interconnect structure, wherein the interconnect layer and the barrier material form a coplanar surface to prevent dishing or divots in the interconnect structure.
2 . The semiconductor device of claim 1 , wherein the coplanar surface includes materials from the dielectric layer, the barrier material and the interconnect layer.
3 . The semiconductor device of claim 1 , wherein the barrier material includes one or more of Ta, TaN, TiN or alloys thereof.
4 . The semiconductor device of claim 1 , wherein the barrier material prevents materials from the interconnect layer from diffusing into the dielectric layer.
5 . The semiconductor device of claim 1 , further comprising a seed layer, the seed layer being disposed between the barrier material and the interconnect layer such that the coplanar surface includes materials from the dielectric layer, the barrier material, the interconnect layer, and the seed layer.
6 . The semiconductor device of claim 5 , wherein the seed layer includes one or more of cobalt (Co), copper (Cu), ruthenium (Ru) or alloys thereof.
7 . The semiconductor device of claim 1 , wherein the coplanar surface is free from defects.
8 . The semiconductor device of claim 1 , wherein the dielectric layer includes an ultralow dielectric-k (ULK) material.
9 . The semiconductor device of claim 8 , wherein the ULK material includes a mix of SiCOH with some porosity.
10 . The semiconductor device of claim 1 , wherein the interconnect layer includes one or more of cobalt (Co), copper (Cu) or alloys thereof.
11 . A semiconductor device, comprising:
a dielectric layer having at least one trench formed therein;
a barrier layer formed on the dielectric layer, the barrier layer being disposed on sidewalls and horizontal surfaces of the at least one trench;
a metallization layer electroplated in the at least one trench to form an interconnect structure; and
a seed layer, the seed layer being disposed between the barrier layer and the metallization layer, wherein the metallization layer, the seed layer, and the barrier layer form a coplanar surface to prevent dishing or divots in the interconnect structure.
12 . The semiconductor device of claim 11 , wherein the barrier layer includes one or more of Ta, TaN, TiN or alloys thereof.
13 . The semiconductor device of claim 11 , wherein the barrier layer prevents materials from the metallization layer from diffusing into the dielectric layer.
14 . The semiconductor device of claim 11 , wherein the coplanar surface includes materials from the dielectric layer, the barrier layer, the metallization layer, and the seed layer.
15 . The semiconductor device of claim 11 , wherein the seed layer includes one or more of cobalt (Co), copper (Cu), ruthenium (Ru) or alloys thereof.
16 . The semiconductor device of claim 11 , wherein the coplanar surface is free from defects.
17 . The semiconductor device of claim 11 , wherein the dielectric layer includes an ultralow dielectric-k (ULK) material.
18 . The semiconductor device of claim 17 , wherein the ULK material includes a mix of SiCOH with some porosity.
19 . The semiconductor device of claim 11 , wherein the metallization layer includes one or more of cobalt (Co), copper (Cu) or alloys thereof.