SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
1 . A method, comprising:
forming raised source and drain regions adjacent to a first gate stack;
forming raised source and drain regions adjacent to a second gate stack; and
forming sidewall spacer material on a sidewall of the first gate stack and a sidewall of the second gate stack,
wherein side surfaces of the raised source and drain regions for the second gate stack contact a side surface of a liner material covering a portion of the second gate stack and a side surface of a spacer material formed on the second gate stack which is not covered by the liner material.
2 . The method of claim 1 , wherein the first gate stack is a PFET and the second gate stack is an NFET.
3 . The method of claim 1 , wherein side surfaces of the raised source and drain regions for the first gate stack contact a liner material covering a portion of the first gate stack, and wherein the side surfaces of the raised source and drain regions for the first gate stack are separated from the sidewall spacer material formed on the first gate stack by the liner material covering the portion of the first gate stack.
4 . The method of claim 3 , further comprising forming a space between the raised source and drain regions and the spacer material of the first gate stack by thinning the spacer material on the sidewalls of the first gate stack by an isotropic etching process.
5 . The method of claim 4 , wherein the isotropic etching process comprises a chemistry of hydrofluoric ethylene glycol (HFEG) which is selective to SiN based spacer material.
6 . The method of claim 4 , wherein the isotropic etching process comprises an HF-based wet chemistry for wet isotropic processes.
7 . The method of claim 4 , wherein the isotropic etching process comprises an isotropic dry etch process used with NF 3 /NH 3 or NH 3 /HF based reactants.
8 . The method of claim 4 , wherein the space has a width dependent on a thickness of the liner material covering the portion of the first gate stack.
9 . The method of claim 4 , wherein the liner material of the first gate stack extends into the space between the raised source and drain regions and the spacer material of the first gate stack to contact the upper surface of a fin structure formed on a semiconductor substrate and under the first gate stack.
10 . The method of claim 9 , wherein the liner material of the first gate stack has a lower dielectric constant than a dielectric constant of the spacer material of the first gate stack.
11 . The method of claim 1 , wherein the spacer material formed on the second gate stack is provided in a blanket deposition process to a thickness of about 3 nm to 15 nm and the liner material covering the portion of the second gate stack is provided in a blanket deposition process to a thickness of about 1 nm to 5 nm.
12 . The method of claim 1 , further comprising forming the raised source and drain regions for the second gate stack, abutting sidewall spacers of the second gate stack, wherein the raised source and drain regions of the first gate stack and the second gate stack are formed by an epitaxial growth process of semiconductor material, which is doped in-situ on the semiconductor substrate.