CHIP-ON-CHIP STRUCTURE AND METHODS OF MANUFACTURE
Sintered connection structures and methods of manufacture are disclosed. The method includes placing a powder on a substrate and sintering the powder to form a plurality of pillars. The method further includes repeating the placing and sintering steps until the plurality of pillars reach a predetermined height. The method further includes forming a solder cap on the plurality of pillars. The method further includes joining the substrate to a board using the solder cap.
1 . A method, comprising:
placing a semiconductor substrate wafer in a chuck;
coating the semiconductor substrate wafer with a plurality of layers of powder, followed by the laser sintering after each coating to form pillars directly in contact with the semiconductor substrate wafer;
joining a chip to the semiconductor substrate wafer between the pillars;
dicing the semiconductor substrate wafer to form a plurality chips with the pillars;
bonding a chip without the pillars to a substrate of another chip of a plurality of chips between the pillars;
the chip without the pillars including plating of micro-bumps; and
bonding an organic laminate to the another chip by the pillars by a reflow of a solder cap.
2 . The method of claim 1 , wherein the reflow is at a reflow temperature of about 250° C. to about 260° C.
3 . The method of claim 1 , wherein:
the powder is a copper powder;
the solder cap is formed by a powder deposition followed by a sintering process; and
the sintering is a laser sintering process.
4 . The method of claim 3 , wherein the solder cap is reflowed, prior to the joining.
5 . The method of claim 1 , further comprising removing any non-sintered powder from the semiconductor substrate wafer, prior to the joining.
6 . The method of claim 1 , wherein a height of the plurality of pillars is greater than 75 μm.
7 . The method of claim 6 , wherein the height of the plurality of pillars is about 500 μm.
8 . The method of claim 1 , wherein the plurality of pillars are tapered.
9 . The method of claim 1 , wherein the plurality of pillars are shaped as an hourglass.
10 . The method of claim 1 , wherein the powder is an insulator material.
11 . A method, comprising:
coating a wafer with a plurality of layers of conductive powder, followed by a laser sintering after each coating to form conductive pillars of a predetermined height directly in contact with the wafer;
forming a solder cap on the conductive pillars;
joining a chip to the wafer between the conductive pillars;
joining a wafer to an organic laminate board by a bonding process of the solder cap of the conductive pillars;
dicing the wafer to form a plurality chips with the conductive pillars;
bonding the chip without the conductive pillars to a substrate of another chip of the plurality of chips between the conductive pillars by a reflow of the solder cap;
the chip without the conductive pillars including plating of micro-bumps; and
the chip without the conductive pillars being bonded to the substrate by a reflow process;
12 . The method of claim 11 , wherein the conductive powder is copper and the solder cap is formed by: deposited solder powder, sintering the solder powder and reflowing the sintered solder powder.
13 . The method of claim 11 , wherein the joining of the chip to the wafer is by reflow or thermocompression bonding.
14 . The method of claim 11 , wherein the predetermined height is greater than 75 μm.
15 . The method of claim 14 , wherein the predetermined height is approximately 500 um.
16 . The method of claim 11 , further comprising underfilling spaces between the chip, wafer and board.
17 . The method of claim 11 , wherein the conductive pillars are shaped as one of (i) cones with its bases being wider in diameter than its end at the solder cap, and (ii) hourglasses.
18 . The method of claim 11 , wherein the joining the wafer to the board is provided by a reflow process.
19 . The method of claim 11 , wherein the reflow is at a reflow temperature of about 250° C. to about 260° C.