FIELD EFFECT TRANSISTOR INCLUDING STRAINED GERMANIUM FINS
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.
1 . A device comprising:
a p-type field effect transistor region including a first fin comprising compressive strained germanium grown on a first mandrel; and
an n-type field effect transistor region including a second fin comprising tensile strained germanium grown on a second mandrel.
2 . The device of claim 1 , wherein the first mandrel comprises silicon germanium.
3 . The device of claim 2 , wherein the silicon germanium is strain relaxed silicon germanium.
4 . The device of claim 3 , wherein an end of the first fin is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end of the first fin directly contact the shallow trench isolation layer.
5 . The device of claim 4 , wherein a second side of the end of the first fin includes a lower portion that directly contacts the relaxed silicon germanium and an upper portion that directly contacts the shallow trench isolation layer.
6 . The device of claim 1 , wherein the second mandrel comprises a Group III-V semiconductor material.
7 . The device of claim 6 , wherein the Group III-V semiconductor material is a strain relaxed Group III-V semiconductor material.
8 . The device of claim 7 , wherein an end of the second fin is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end directly contact the shallow trench isolation layer.
9 . The device of claim 8 , wherein a second side of the end of the second fin includes a lower portion that directly contacts the strain relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
10 . The device of claim 6 , wherein the Group III-V semiconductor material comprises:
a layer of gallium arsenide; and
a layer of indium gallium arsenide deposited over the layer of gallium arsenide.
11 . A device comprising:
a p-type field effect transistor region, comprising:
a first mandrel comprising relaxed silicon germanium; and
a first fin grown on a sidewall of the first mandrel and comprising compressive strained germanium; and
an n-type field effect transistor region, comprising:
a second mandrel comprising at least one relaxed Group III-V semiconductor material; and
a second fin grown on a sidewall of the second mandrel and comprising tensile strained germanium.
12 . The device of claim 11 , wherein the first fin comprises:
an end that is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end directly contact the shallow trench isolation layer, and a second side of the end includes a lower portion that directly contacts the relaxed silicon germanium and an upper portion that directly contacts the shallow trench isolation layer.
13 . The device of claim 11 , wherein the second fin comprises:
an end that is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the end directly contact the shallow trench isolation layer, and a second side of the end includes a lower portion that directly contacts the relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
14 . A method for fabricating a device, the method comprising:
forming a first mandrel in a p-type field effect transistor region of the device;
forming a second mandrel in an n-type field effect transistor region of the device;
growing a compressive strained germanium fin on a sidewall of the first mandrel; and
growing a tensile strained germanium fin on a sidewall of the second mandrel.
15 . The method of claim 14 , wherein the first mandrel and the second mandrel are formed using aspect ratio trapping.
16 . The method of claim 14 , wherein the first mandrel comprises silicon germanium.
17 . The method of claim 16 , wherein the silicon germanium is strain relaxed silicon germanium.
18 . The method of claim 14 , wherein the second mandrel comprises at least one Group III-V semiconductor material.
19 . The method of claim 18 , wherein the at least one Group III-V semiconductor material is a strain relaxed Group III-V semiconductor material.
20 . The method of claim 19 , wherein the at least one Group III-V semiconductor material comprises:
a layer of gallium arsenide; and
a layer of indium gallium arsenide deposited over the layer of gallium arsenide.