Semiconductor device with buried local interconnects
Embodiments of the present invention provide methods for fabricating a semiconductor device with buried local interconnects. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a first set of spacers along the sides of the fins; depositing a tungsten film over the top surface of the substrate; etching the tungsten film to form a buried local interconnect; forming a set of gates and a second set of spacers; forming a source and drain region adjacent to the fins; depositing a first insulating material over the top surface of the substrate; and creating contact between the set of gates and the source and drain region using an upper buried local interconnect.
1. A semiconductor structure comprising:
a plurality of fins patterned in a starting semiconductor substrate;
an insulator and a first set of spacers, wherein the insulator and the first set of spacers are recessed to a same level;
a source and drain region formed around the plurality of fins;
a gate structure and a second set of spacers, wherein a portion of the gate structure and the second set of spacers are disposed around the plurality of fins; and
a buried local interconnect wire, wherein the buried local interconnect wire includes a buried local interconnect and an upper buried local interconnect.
2. The semiconductor structure of claim 1 , wherein the upper buried local interconnect is configured to provide an electrical connection between the gate structure and the source and drain region.
3. The semiconductor structure of claim 1 , wherein the upper buried local interconnect is configured to provide an electrical connection between the source and drain region and the buried local interconnect.
4. The semiconductor structure of claim 1 , wherein the starting semiconductor substrate comprises one or more of: Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, silicon doped with carbon, amorphous Si, semiconductor materials, and compound semiconductor substrates.
5. The semiconductor structure of claim 1 , wherein the plurality of fins are etched to a depth of 100 nm.
6. The semiconductor structure of claim 1 , wherein the buried local interconnect comprises tungsten.
7. The semiconductor structure of claim 1 , wherein the insulator comprises a silicon oxide or a silicon nitride.
8. The semiconductor structure of claim 1 , wherein the gate structure comprises at least one layer of a gate dielectric and at least one metal.
9. The semiconductor structure of claim 1 , wherein the insulator and the first set of spacers are recessed to a level of greater than or equal to 20 nm and less than or equal to 30 nm.
10. The semiconductor structure of claim 1 , wherein the gate structure comprises a dummy gate or an actual gate.