SELF-ALIGNED SPACER FOR CUT-LAST TRANSISTOR FABRICATION
Semiconductor devices include one or more semiconductor fins. A gate dielectric is formed over the one or more semiconductor fins. A gate is formed over the gate dielectric. A dummy gate dielectric remnant is formed adjacent to the gate dielectric. A vertical sidewall is disposed on the dummy gate dielectric remnant. The vertical sidewall has a uniform thickness along its height.
1 . A semiconductor device, comprising:
one or more semiconductor fins;
a gate dielectric formed over the one or more semiconductor fins;
a gate formed over the gate dielectric;
a dummy gate dielectric remnant formed adjacent to the gate dielectric; and
a vertical sidewall on the dummy gate dielectric remnant, the vertical sidewall having a uniform thickness along its height.
2 . The semiconductor device of claim 1 , wherein the vertical sidewall is formed from silicon nitride.
3 . The semiconductor device of claim 2 , wherein there is no silicon nitride on horizontal surfaces around a base of the vertical sidewall.
4 . The semiconductor device of claim 1 , wherein the gate dielectric is formed between the gate and the one or more semiconductor fins.
5 . The semiconductor device of claim 1 , wherein the gate dielectric and the dummy gate dielectric remnant are formed from different materials.
6 . The semiconductor device of claim 5 , wherein the gate dielectric is formed from a high-k dielectric material and wherein the dummy gate dielectric remnant is formed from silicon dioxide.
7 . The semiconductor device of claim 1 , further comprising an upper spacer that is formed continuous with, and from a same material as, the vertical sidewall.
8 . The semiconductor device of claim 7 , wherein the upper spacer and the vertical sidewall together encapsulate the gate.
9 . The semiconductor device of claim 7 , further comprising a gate contact that pierces the upper spacer to make electrical contact with the gate.
10 . A semiconductor device, comprising:
one or more semiconductor fins;
a vertical sidewall forming a perimeter and having a uniform thickness along its height;
a gate dielectric formed on the one or more semiconductor fins;
a gate formed over the gate dielectric;
a dummy gate dielectric remnant formed directly underneath the vertical sidewall, adjacent to the gate dielectric; and
a power rail in contact with the vertical sidewall.
11 . The semiconductor device of claim 10 , wherein the vertical sidewall is formed from silicon nitride.
12 . The semiconductor device of claim 10 , wherein there is no silicon nitride on horizontal surfaces around a base of the vertical sidewall.
13 . The semiconductor device of claim 10 , wherein the gate dielectric and the dummy gate dielectric remnant are formed from different materials.
14 . The semiconductor device of claim 13 , wherein the gate dielectric is formed from a high-k dielectric material and wherein the dummy gate dielectric remnant is formed from silicon dioxide.
15 . The semiconductor device of claim 10 , further comprising an upper spacer that is formed continuous with, and from a same material as, the vertical sidewall.
16 . The semiconductor device of claim 15 , wherein the upper spacer and the vertical sidewall together encapsulate the gate.
17 . The semiconductor device of claim 15 , further comprising a gate contact that pierces the upper spacer to make electrical contact with the gate.
18 . A semiconductor device, comprising:
one or more semiconductor fins;
a silicon nitride vertical sidewall forming a perimeter and having a uniform thickness along its height;
a high-k gate dielectric formed on the one or more semiconductor fins and on an inner side of the vertical sidewall;
a gate formed over the gate dielectric;
a silicon dioxide upper spacer that is formed continuous with the vertical sidewall, wherein the upper spacer and the vertical sidewall together encapsulate the gate;
a silicon dioxide dummy gate dielectric remnant formed directly underneath the vertical sidewall and adjacent to the high-k gate dielectric; and
a power rail in contact with the vertical sidewall.
19 . The semiconductor device of claim 18 , wherein there is no silicon nitride on horizontal surfaces around a base of the vertical sidewall.
20 . The semiconductor device of claim 18 , wherein the silicon dioxide dummy gate dielectric remnant extends horizontally beyond the silicon nitride vertical sidewall.