Semiconductor structure with integrated passive structures
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.
1. A structure comprising:
an active device comprising:
a high-k dielectric material on a substrate;
a metal material on the high-k dielectric material; and
a semiconductor material over the metal material;
a passive structure comprising a semiconductor layer in contact with an upper surface of a shallow trench isolation structure, adjacent to the active device; and
a liner formed on a lower surface of the shallow trench isolation structure and between a sidewall of the shallow trench isolation structure and respective sidewalls of each of the substrate, the high-k dielectric material, the metal material and the semiconductor material.
2. The structure of claim 1 , wherein ion implanting dopant impurities penetrate into a substrate to form wells in the substrate of the active device.
3. The structure of claim 1 , wherein the semiconductor layer is directly on the shallow trench isolation structures.
4. The structure of claim 1 , wherein the semiconductor material is recessed in the active region.
5. The structure of claim 1 , wherein the semiconductor material is protruding in the active region.
6. The structure of claim 1 , wherein the metal material is a gate metal.
7. The structure of claim 1 , wherein the gate metal is one of TiN, TaN, Al, and W deposited to a thickness ranging from about 1 nm to about 200 nm.
8. The structure of claim 1 , wherein the liner is in direct contact with the sidewall of the substrate.
9. The structure of claim 8 , wherein the substrate is a silicon-on-insulator layer formed on an oxide layer.
10. The structure of claim 9 , wherein the oxide layer underlies the shallow trench isolation structure, and wherein the liner on the lower surface of the shallow trench isolation structure separates the lower surface of the shallow trench isolation structure from the oxide layer.
11. The structure of claim 10 , wherein the liner is comprised of at least one material from a group consisting of: silicon nitride; and silicon oxynitride.
12. The structure of claim 11 , wherein the liner has a thickness of 10 Å-200 Å.
13. The structure of claim 8 , wherein the liner on the sidewall of the shallow trench isolation structure is separated from the high-k dielectric material, the sidewall of the metal material and the sidewall of the semiconductor material by an insulating layer.
14. The structure of claim 13 , wherein the insulating layer is a compressive stress insulator.
15. The structure of claim 13 , wherein the insulating layer is a tensile stress insulator.
16. The structure of claim 13 , wherein the insulating layer is a neutral stress insulator.
17. The structure of claim 13 , wherein the insulating layer covers upper surfaces of the substrate, the active device and the passive structure.