Methods and structures for forming uniform fins when using hardmask patterns

1. A method for manufacturing a semiconductor device, comprising:

forming a plurality of patterned hardmask portions on a substrate, wherein each of the patterned hardmask portions are spaced apart from each other along the substrate in a horizontal direction with respect to a top surface of the substrate;

forming a plurality of patterned dummy hardmask portions on the substrate which includes

conformally depositing a dummy hardmask layer on the substrate and on the plurality of patterned hardmask portions,

patterning the dummy hardmask layer to form the plurality of patterned dummy hardmask portions,

wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions; and

etching portions of the substrate to form a plurality of fins and a plurality of dummy fins from the substrate, wherein the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions are used as masks during the etching.

2. The method according to claim 1 , wherein the plurality of patterned dummy hardmask portions comprise a material which has an etch selectivity with respect to a material of the patterned hardmask portions.

3. The method according to claim 1 , wherein a distance between a patterned dummy hardmask portion and an adjacent outermost patterned hardmask portion is the same or substantially the same as a distance between two adjacent patterned hardmask portions.

4. The method according to claim 1 , wherein a critical dimension of a patterned dummy hardmask portion is the same or substantially the same as a critical dimension of a patterned hardmask portion.

5. The method according to claim 1 , wherein forming the plurality of patterned dummy hardmask portions further comprises forming a spacer layer on the dummy hardmask layer.

6. The method according to claim 5 , wherein forming the plurality of patterned dummy hardmask portions further comprises removing portions of the spacer layer to form a plurality of spacers on the dummy hardmask layer.

7. The method according to claim 6 , wherein the plurality of spacers cover portions of the dummy hardmask layer, and wherein forming the plurality of patterned dummy hardmask portions further comprises removing remaining portions of the dummy hardmask layer not covered by the plurality of spacers.

8. The method according to claim 6 , wherein a distance between a spacer of the plurality of spacers and an adjacent patterned hardmask portion is the same or substantially the same as a distance between two adjacent patterned hardmask portions.

9. The method according to claim 1 , wherein the etching is performed to a depth including an active height of the plurality of fins.

10. The method according to claim 9 , further comprising selectively removing the plurality of patterned dummy hardmask portions from the plurality of dummy fins with respect to the plurality of patterned hardmask portions.

11. The method according to claim 10 , further comprising further etching remaining portions of the substrate not covered by the plurality of patterned hardmask portions, including the plurality of dummy fins, to a depth below the active height of the plurality of fins.

12. The method according to claim 11 , further comprising forming a dielectric layer on the substrate to a height below the active height of the plurality of fins.

13. The method according to claim 1 , wherein a critical dimension of each of the plurality of fins is the same or substantially the same.

14. A method for manufacturing a semiconductor device, comprising:

forming a plurality of patterned hardmask portions on a substrate, wherein each of the patterned hardmask portions are spaced apart from each other along the substrate in a horizontal direction with respect to a top surface of the substrate;

forming a plurality of patterned dummy hardmask portions on the substrate which includes

conformally depositing a dummy hardmask layer on the substrate and on the plurality of patterned hardmask portions,

patterning the dummy hardmask layer to form the plurality of patterned dummy hardmask portions,

wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions;

etching portions of the substrate to form a plurality of fins under the plurality of patterned hardmask portions and a plurality of dummy fins under the plurality of patterned dummy hardmask portions, wherein the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions are used as masks during the etching; and selectively removing the plurality of patterned dummy hardmask portions from the plurality of dummy fins with respect to the plurality of patterned hardmask portions.

15. The method according to claim 14 , wherein the etching is performed to a depth including an active height of the plurality of fins.

16. The method according to claim 14 , further comprising further etching remaining portions of the substrate not covered by the plurality of patterned hardmask portions, including the plurality of dummy fins, to a depth below the active height of the plurality of fins.

17. The method according to claim 14 , wherein a distance between a patterned dummy hardmask portion and an adjacent outermost patterned hardmask portion is the same or substantially the same as a distance between two adjacent patterned hardmask portions.

18. The method according to claim 14 , wherein forming the plurality of patterned dummy hardmask portions further comprises forming a spacer layer on the dummy hardmask layer.