Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering
A method of forming fin structures that includes providing at least one silicon germanium containing fin structure, and forming a fin liner on the at least one silicon germanium containing fin structure. The fin liner includes a silicon germanium and oxygen containing layer. The method continues with annealing the at least on silicon germanium containing fin structure having the fin liner present thereon. During the annealing, the silicon germanium oxygen containing layer reacts with the silicon germanium containing fin structure to provide surface formation of a silicon rich layer on the silicon germanium containing fin structure.
1. A semiconductor device comprising:
at least one silicon germanium containing fin structure on a supporting substrate having a surface layer on an upper portion of the fin structure that is opposite a base of the fin structure, the surface layer being a silicon rich layer that is present on a channel portion and source and drain region portions of said at least one silicon germanium containing fin structure;
a fin liner present along sidewalls of a lower portion of said at least one silicon germanium containing fin structure, the fin liner present between the silicon rich layer and the supporting substrate;
a gate structure present on the channel portion of the at least one silicon germanium containing fin structure; and
source and drain regions of epitaxial semiconductor material on the source and drain region portions of said at least one silicon germanium containing fin structure.
2. The semiconductor device of claim 1 , wherein the fin liner comprises a layer of silicon germanium oxide (SiGeOx) that is present on the at least one silicon germanium containing fin structure.
3. The semiconductor device of claim 2 , wherein the fin liner further comprises a silicon nitride containing layer present on the layer of silicon germanium oxide.
4. The semiconductor device of claim 1 , wherein the fin liner has a total thickness ranging from 1 nm to 10 nm.
5. The semiconductor device of claim 1 , wherein the silicon rich layer comprises greater than 95 at. % silicon.
6. The semiconductor device of claim 5 , wherein the silicon rich layer has a thickness ranging from 1 monolayer to seven monolayers of silicon atoms.
7. The semiconductor device of claim 6 , wherein the at least one silicon germanium containing fin structure is silicon germanium (SiGe).
8. A semiconductor device comprising:
at least one silicon germanium fin structure having an upper portion with a surface layer being a silicon rich layer that is present on a channel portion and source and drain region portions of said at least one silicon germanium containing fin structure;
a fin liner present along sidewalls of a lower portion of said at least one silicon germanium fin structure that are positioned between the silicon rich layer and a supporting substrate;
a gate structure present on the channel portion of the at least one silicon germanium fin structure; and
source and drain regions on the source and drain region portions of said at least one silicon germanium fin structure.
9. The semiconductor device of claim 8 , wherein the fin liner comprises a layer of silicon germanium oxide (SiGeOx).
10. The semiconductor device of claim 9 , further comprising a silicon nitride layer present on the layer of silicon germanium oxide.
11. The semiconductor device of claim 8 , wherein the fin liner has a total thickness ranging from 1 nm to 10 nm.
12. The semiconductor device of claim 8 , wherein the silicon rich layer comprises greater than 95 at. % silicon.
13. The semiconductor device of claim 8 , wherein the silicon rich layer has a thickness ranging from 1 monolayer to seven monolayers of silicon atoms.
14. A semiconductor device comprising:
at least one silicon germanium fin structure having an upper portion with a surface layer being a silicon rich layer that is present on a channel portion and source and drain region portions of said at least one silicon germanium containing fin structure;
a fin liner of comprises a layer of silicon germanium oxide (SiGeOx) present on a lower portion of the at least one silicon germanium fin structure along sidewalls of said at least one silicon germanium fin structure between the silicon rich layer and a supporting substrate; and
a gate structure present on the channel portion of the at least one silicon germanium fin structure.
15. The semiconductor device of claim 14 , wherein the fin liner further comprises a silicon nitride layer present on the layer of silicon germanium oxide.
16. The semiconductor device of claim 14 , wherein the fin liner has a total thickness ranging from 1 nm to 10 nm.
17. The semiconductor device of claim 16 , wherein the silicon rich layer comprises greater than 95 at. % silicon.
18. The semiconductor device of claim 14 , wherein the silicon rich layer has a thickness ranging from 1 monolayer to seven monolayers of silicon atoms.
19. The semiconductor device of claim 18 , wherein the gate structure comprises a p-type work function layer or an n-type work function layer.
20. The semiconductor device of claim 14 , further comprising source and drain regions of epitaxial semiconductor material on opposing sides of the channel region.