Gate height and spacer uniformity
Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method includes forming a first sacrificial gate adjacent to a second sacrificial gate on a substrate. A dielectric layer is formed on the substrate and above top surfaces of the first and second sacrificial gates. A self-aligned protection region is formed to cover a first portion of the dielectric layer and a second uncovered portion of the dielectric layer is removed. The first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.
1. A method for forming a semiconductor device, the method comprising:
forming a sacrificial gate on a substrate;
forming a dielectric layer comprising a first portion and a second portion, the dielectric layer on the substrate and above a top surface of the sacrificial gate, the first portion in direct contact with sidewalls of the sacrificial gate and between the sidewalls of the sacrificial gate and the second portion;
recessing the dielectric layer;
forming a self-aligned protection region to cover the first portion of the dielectric layer; and
removing the second portion of the dielectric layer to expose a surface of the substrate.
2. The method of claim 1 , wherein the first portion of the dielectric layer defines a spacer after the second portion of the dielectric layer is removed.
3. The method of claim 2 further comprising forming a hard mask on a top surface of the sacrificial gate.
4. The method of claim 3 further comprising removing the hard mask; wherein the self-aligned protection region protects the spacer while the hard mask is removed.
5. The method of claim 3 , wherein forming the self-aligned protection region further comprises:
forming a protection layer over the first and second portions of the dielectric layer and the hard mask; and
removing portions of the protection layer to expose the second portion of the dielectric layer, the remaining portion of the protection layer defining the self-aligned protection region.
6. The method of claim 2 further comprising forming a doped region on the substrate adjacent to the sacrificial gate.
7. The method of claim 6 further comprising forming a second dielectric layer over the doped region and the hard mask.
8. The method of claim 7 further comprising removing portions of the second dielectric layer to expose a portion of the spacer.
9. The method of claim 8 further comprising forming a third dielectric layer on the second dielectric layer and the spacer.
10. The method of claim 9 further comprising:
removing the self-aligned protection region and portions of the third dielectric layer to expose a top surface of the spacer; and
removing the sacrificial gate.
11. The method of claim 2 , wherein the spacer is a self-aligned low-k dielectric spacer.
12. The method of claim 2 , wherein the spacer comprises a silicon nitride, a silicon oxynitride (SiON), a silicon carbide (SiC), a silicon oxygen carbonitride (SiOCN), or a silicoboron carbonitride (SiBCN).
13. The method of claim 1 , wherein the self-aligned protection region comprises silicon dioxide (SiO 2) .
14. The method of claim 2 , wherein a thickness of the spacer is about 10 nm to about 30 nm.
15. A method for forming a semiconductor device, the method comprising:
forming a sacrificial gate on a substrate, the sacrificial gate comprising a hard mask, a sidewall spacer, and a self-aligned protection region formed over the sidewall spacer and adjacent to the hard mask; and
removing the hard mask, the self-aligned protection region protecting the sidewall spacer while the hard mask is removed.
16. The method of claim 15 further comprising forming a doped region on the substrate and adjacent to the sacrificial gate.
17. The method of claim 16 further comprising forming a second dielectric layer over the doped region.
18. The method of claim 17 further comprising recessing the second dielectric layer to expose a portion of the sidewall spacer.
19. The method of claim 18 further comprising forming a third dielectric layer on the recessed second dielectric layer.
20. The method of claim 19 further comprising removing the self-aligned protection region and portions of the third dielectric layer to expose a top surface of the sidewall spacer.