WELL AND PUNCH THROUGH STOPPER FORMATION USING CONFORMAL DOPING
A method for doping fins includes depositing a first dopant layer at a base of fins formed in a substrate, depositing a dielectric layer on the first dopant layer and etching the dielectric layer and the first dopant layer in a first region to expose the substrate and the fins. A second dopant layer is conformally deposited over the fins and the substrate in the first region. The second dopant layer is recessed to a height on the fins in the first region. An anneal is performed to drive dopants into the fins from the first dopant layer in a second region and from the second dopant layer in the first region to concurrently form punch through stoppers in the fins and wells in the substrate.
1 . A fin field effect transistor device, comprising:
a first dopant layer formed at a base of fins and on a substrate supporting the fins in a first region;
a cap layer formed on first dopant layer, the first dopant layer and the cap layer disposed below a punch through stopper height on the fins;
a second dopant layer formed at a base of fins and on the substrate supporting the fins in a second region, the second dopant layer disposed below a punch through stopper height on the fins;
a first well formed in the substrate in the first region below the first dopant layer;
a second well formed in the substrate in the second region below the second dopant layer; and
a field dielectric formed from the base of the fins to a top of punch through stoppers in the first and second regions.
2 . The device as recited in claim 1 , wherein the first dopant layer includes a doped silicate glass with a dopant conductivity of a first type and the second dopant layer includes a doped silicate glass with a dopant conductivity of a second type.
3 . The device as recited in claim 1 , wherein the first region includes one of an n-type field effect transistor (NFET) region or a p-type field effect transistor (PFET) region and the second region includes the other of the NFET region or the PFET region.
4 . The device as recited in claim 1 , wherein the punch through stoppers in the fins are formed concurrently with respective first and second wells.
5 . The device as recited in claim 1 , wherein the first dopant layer and the second dopant layer include different dopant conductivity types.
6 . The device as recited in claim 1 , wherein the first well and the second well include different dopant conductivity types.
7 . The device as recited in claim 1 , wherein the field dielectric is disposed over the first and second dopant layers.
8 . The device as recited in claim 1 , further comprising a hard mask layer disposed over horizontal portions of the fins.
9 . The device of claim 8 , wherein the hard mask layer includes nitride.
10 . The device as recited in claim 1 , wherein the fins include crystalline silicon.
11 . The device as recited in claim 1 , wherein the cap layer includes silicon nitride.
12 . The device as recited in claim 1 , wherein the field dielectric includes a field oxide.