FIELD EFFECT TRANSISTOR GATE STACK
A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, depositing a first nitride layer on exposed portions of the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer, the scavenging layer, and the first nitride layer to expose a portion of the first dielectric layer in an n-type field effect transistor (nFET) region of the gate stack, forming a barrier layer over the first dielectric layer and the capping layer, forming a first gate metal layer over the barrier layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.
1 . A semiconductor device comprising a gate stack arranged over a channel region of the device, the gate stack comprising an n-type field effect transistor (nFET) portion comprising:
a dielectric layer arranged on a substrate;
a barrier layer arranged on the dielectric layer;
a first gate metal layer arranged on the barrier layer;
a first nitride layer arranged on the first gate metal layer; and
a gate electrode arranged on the second nitride layer.
2 . The semiconductor device of claim 1 , further comprising a p-type field effect transistor (pFET) portion.
3 . The semiconductor device of claim 2 , wherein the pFET portion comprises:
the dielectric layer arranged on the substrate;
a second nitride layer arranged on the dielectric layer;
a scavenging layer arranged on the second nitride layer;
a capping layer arranged on the scavenging layer;
a barrier layer arranged on the capping layer;
the first gate metal layer arranged on the barrier layer;
the first nitride layer arranged on the first gate metal layer; and
the gate electrode arranged on the second nitride layer.
4 . The semiconductor device of claim 1 , wherein the dielectric layer includes an oxide material.
5 . The semiconductor device of claim 1 , wherein the barrier layer includes a metal nitride material.
6 . The semiconductor device of claim 1 , wherein the gate electrode material includes tungsten.
7 . The semiconductor device of claim 1 , wherein the first gate metal layer includes TiAlC.
8 . The semiconductor device of claim 1 , wherein the first gate metal layer includes TiAl.
9 . The semiconductor device of claim 1 , wherein the first nitride layer includes TiN.
10 . The semiconductor device of claim 1 , wherein the first nitride layer includes TaN.
11 . The semiconductor device of claim 1 , wherein the second nitride layer includes TiN.
12 . A semiconductor device comprising:
a gate stack arranged over a channel region of the device, the gate stack comprising:
an n-type field effect transistor (nFET) portion comprising:
a dielectric layer arranged on a substrate;
a barrier layer arranged on the dielectric layer;
a first gate metal layer arranged on the barrier layer;
a first nitride layer arranged on the first gate metal layer; and
a gate electrode arranged on the second nitride layer; and
a p-type field effect transistor (pFET) portion comprising:
the dielectric layer arranged on the substrate;
a second nitride layer arranged on the dielectric layer;
a scavenging layer arranged on the second nitride layer;
a capping layer arranged on the scavenging layer;
a barrier layer arranged on the capping layer;
the first gate metal layer arranged on the barrier layer;
the first nitride layer arranged on the first gate metal layer; and
the gate electrode arranged on the second nitride layer.
13 . The semiconductor device of claim 12 , wherein the dielectric layer includes an oxide material.
14 . The semiconductor device of claim 12 , wherein the barrier layer includes a metal nitride material.
15 . The semiconductor device of claim 12 , wherein the gate electrode material includes tungsten.
16 . The semiconductor device of claim 12 , wherein the first gate metal layer includes TiAlC.
17 . The semiconductor device of claim 12 , wherein the first gate metal layer includes TiAl.
18 . The semiconductor device of claim 12 , wherein the first nitride layer includes TiN.
19 . The semiconductor device of claim 12 , wherein the first nitride layer includes TaN.
20 . The semiconductor device of claim 12 , wherein the second nitride layer includes TiN.