SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
1 . A structure, comprising:
a first gate structure and a second gate structure formed over a fin structure;
raised source and drain regions formed adjacent to the first gate structure; and
raised source and drain regions formed adjacent to the second gate structure,
wherein side surfaces of the raised source and drain regions of the first gate structure contact a first liner material covering a portion of the first gate structure, which first liner material extends to an upper surface of the fin structure,
wherein the side surfaces of the raised source and drain regions of the first gate structure are separated from a first spacer material formed on the first gate structure by the first liner material covering the portion of the first gate structure, and
wherein side surfaces of the raised source and drain regions of the second gate structure contact a side surface of a second liner material covering a portion of the second gate structure and a side surface of a second spacer material formed on the second gate structure which is not covered by the second liner material.
2 . The structure of claim 1 , wherein the first gate structure is a gate structure of an N-type FET (NFET) and the second gate structure is a gate structure of a P-type FET (PFET).
3 . The structure of claim 2 , wherein:
the first liner material and first spacer material formed on the first gate structure form a first sidewall spacer on a side surface of the first gate structure;
the second liner material and second spacer material formed on the second gate structure form a second sidewall spacer on a side surface of the second gate structure; and
the first sidewall spacer and the second sidewall spacer have substantially the same thickness.
4 . The structure of claim 1 , wherein a space is formed between the raised source and drain regions of the first gate structure and the first spacer material of the first gate structure.
5 . The structure of claim 4 , wherein the first liner material of the first gate structure extends into the space between the raised source and drain regions and the first spacer material of the first gate structure to contact the upper surface of the fin structure.
6 . The structure of claim 5 , wherein the first liner material of the first gate structure has a lower dielectric constant than a dielectric constant of the first spacer material of the first gate structure.
7 . The structure of claim 6 , wherein the first gate structure and the second gate structure each include a dielectric layer formed in contact with the upper surface of the fin structure and in contact with inner walls of the first spacer material and the second spacer material, the dielectric layer being spaced apart from the first and second liner materials by the first and second spacer materials, respectively.
8 . The structure of claim 7 , wherein the first gate structure and the second gate structure each include a conductive material formed on the dielectric layer, the conductive material is in contact with inner walls of the first and second spacer materials, the conductive material is spaced apart from the first and second liner materials by the first and second spacer materials, respectively, and the first liner material of the first gate structure extends into the space between the raised source and drain regions of the first gate structure and the first spacer material of the first gate structure to contact the upper surface of the fin structure.
9 . The structure of claim 8 , wherein the first and second liner materials are comprised of at least one of SiN, SiO 2 , SiOCN, SiCN and SiCOH.
10 . The structure of claim 4 , wherein the space has a width dependent on a thickness of the first liner material.
11 . The structure of claim 10 , wherein the first and second spacer materials have a thickness of about 3 nm to 15 nm and the first and second liner materials have a thickness of about 1 nm to 5 nm.
12 . The structure of claim 11 , wherein the raised source and drain regions of the first gate structure and the second gate structure are a doped epitaxial semiconductor material.
13 . The structure of claim 3 , wherein the raised source and drain regions abutting the sidewall spacers of the first and second gate structures are formed on the fin structure.
14 . The structure of claim 13 , wherein the first gate structure and the second gate structure each include a dielectric layer formed in contact with an upper surface of the fin structure and in contact with inner walls of the first and second spacer materials, and the dielectric layer is spaced apart from the first and second liner materials by the first and second spacer materials, respectively.
15 . The structure of claim 14 , wherein the first gate structure and the second gate structure each include a conductive material formed on the dielectric layer, the conductive material is in contact with inner walls of the first and second spacer materials, and the conductive material is spaced apart from the first and second liner materials by the first and second spacer materials, respectively.
16 . The structure of claim 1 , wherein lower surfaces of the raised source and drain regions of the first gate structure and the second gate structure are formed on the upper surface of the fin structure, and wherein a lower surface of the fin structure is formed over a substrate and separated from the substrate by an insulating layer.