Resistor fins
A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.
1. A resistor fin device comprising:
resistor fins formed on a substrate, wherein the resistor fins are formed of a first material and a second material;
a shallow trench isolation material formed between the resistor fins; and
a metal contact layer in direct contact with the resistor fins.
2. The device of claim 1 , wherein the first material is a doped polysilicon material.
3. The device of claim 1 , wherein the second material is an electrically-isolating insulator material.
4. The device of claim 1 , wherein the first material a resistive material with a resistivity value.
5. The device of claim 1 , further comprising a field-effect-transistor formed at a same time as forming the resistor fin device.
6. The device of claim 5 , wherein the field-effect-transistor includes one of the resistor fins.
7. The device of claim 6 , wherein the field-effect-transistor includes source/drain regions formed on other fins, the other fins being formed from the substrate.
8. The device of claim 1 , wherein the metal contact layer comprises a work function setting layer.
9. The device of claim 8 , wherein the work function setting layer comprises nitride.
10. The device of claim 8 , wherein the work function setting layer is selected from the group consisting of titanium nitride (TiN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), and tantalum silicon nitride (TaSiN).
11. The device of claim 8 , wherein the work function setting layer is selected from the group consisting of tungsten nitride (WN), molybdenum nitride (MoN), and niobium nitride (NbN).
12. The device of claim 8 , wherein the work function setting layer comprises carbide.
13. The device of claim 8 , wherein the work function setting layer is selected from the group consisting of titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), and hafnium carbide (HfC).
14. The device of claim 1 , wherein the metal contact layer is located at longitudinal ends of the resistor fins.
15. The device of claim 1 , wherein the shallow trench isolation material comprises oxide.
16. The device of claim 5 , wherein the field-effect-transistor comprises one or more gate structures.
17. The device of claim 16 , wherein the one or more gate structures comprise a high-k dielectric material.
18. The device of claim 16 , wherein the one or more gate structures is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and boron nitride.
19. The device of claim 5 , wherein the field-effect-transistor comprises an epitaxially grown source/drain region.
20. The device of claim 1 , wherein the substrate comprises a semiconductor material.