Enhancement of iso-via reliability
A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.
1. A semiconductor structure comprising:
a semiconductor base comprising a plurality of semiconductor devices;
a back end of the line wiring layer comprising:
a wiring line;
a multilayer cap layer on the wiring line comprising first, second and third layers of silicon carbide nitride (SiCN) such that the second layer is between the first and third layers and is richer in silicon content than the first and third layers and the second layer is oxidized to form a reliability enhancement material comprising silicon carbide nitride plus oxygen (SiOCN);
an interlayer dielectric (ILD) layer on the cap layer and the reliability enhancement material;
a via extending through the ILD, the first layer, the reliability enhancement material and the third layer to communicate with the wiring line; and
a metal filling the via and in contact with the third layer and the reliability enhancement material;
wherein the reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the third layer be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the first and third layers of the cap layer.
2. The semiconductor structure of claim 1 wherein the second layer is at least 5 atomic percent richer in silicon content than the first and third layers.
3. The semiconductor structure of claim 1 wherein the different physical properties includes the reliability enhancement material has a different material composition than the first and third layers.
4. The semiconductor structure of claim 1 wherein the different physical properties includes the reliability enhancement material is compressive and the first and third layers are not compressive.
5. The semiconductor structure of claim 1 wherein the third layer is in direct contact with the wiring line.
6. The semiconductor structure of claim 1 wherein the via has a via wall and further comprising a barrier layer on the via wall between the via wall and the metal filling the via.
7. The semiconductor structure of claim 1 wherein the reliability enhancement material is separate from the first and third layers.
8. A process of making a semiconductor structure comprising:
forming a wiring line;
forming a cap layer on the wiring line, the cap layer being a multiple layer structure with sequential first, second and third layers of the multiple layer structure each comprising silicon, carbon and nitrogen with the second layer having a higher silicon content than the first and third layers;
forming an interlayer dielectric (ILD) layer on the cap layer;
forming a via opening through the ILD layer and the first and second layers of the cap layer to expose the third layer of the cap layer on a surface of the wiring line;
exposing the cap layer to an oxidation environment so that a portion of the second layer is oxidized to form a compound comprising silicon, oxygen, carbon and nitrogen and expands with respect to the first and third layers such that the expanded second layer becomes a reliability enhancement material; and
removing the third layer exposed to the via opening to expose the wiring line;
filling the via opening with a metal to form a metal-filled via in contact with the wiring line;
wherein the reliability enhancement material surrounding the metal-filled via only in the cap layer and the reliability enhancement material causing a compressive stress on the metal-filled via where it contacts the wiring line.
9. The process of claim 8 wherein the second layer is at least 5 atomic percent richer in silicon content than the first and third layers.
10. The process of claim 8 wherein the third layer is in direct contact with the metal filling the via and the wiring line.
11. The semiconductor structure of claim 8 wherein the third layer does not contain the reliability enhancement material.
12. The process of claim 8 wherein the via has a via wall and further comprising a barrier layer on the via wall between the via wall and the metal filling the via.